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|manufacturer 2=GlobalFoundries | |manufacturer 2=GlobalFoundries | ||
|introduction=October 8, 2020 | |introduction=October 8, 2020 | ||
− | |process=7nm | + | |process=7nm |
|cores=64 | |cores=64 | ||
|cores 2=56 | |cores 2=56 | ||
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|extension 27=UMIP | |extension 27=UMIP | ||
|extension 28=CLZERO | |extension 28=CLZERO | ||
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|predecessor=Zen 2 | |predecessor=Zen 2 | ||
|predecessor link=amd/microarchitectures/zen 2 | |predecessor link=amd/microarchitectures/zen 2 | ||
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[[File:amd zen future roadmap.jpg|400px|right]] | [[File:amd zen future roadmap.jpg|400px|right]] | ||
Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. | Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]]. | ||
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== Products == | == Products == | ||
+ | [[File:amd zen2-3 roadmap.png|400px|right]] | ||
{{future information}} | {{future information}} | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! | + | ! Product Line !! Cores/Threads !! Target |
|- | |- | ||
| EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]] | | EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]] | ||
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| {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing | | {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing | ||
|- | |- | ||
− | | | + | | {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors |
|- | |- | ||
| Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors | | Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors | ||
|- | |- | ||
− | | Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with | + | | Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with GPU |
|} | |} | ||
== Process technology == | == Process technology == | ||
− | Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]] | + | Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]], the same process used in Zen 2 Refresh processors. |
− | + | == Architecture == | |
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− | == | ||
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− | + | There is very limited information available about the architectural improvements of Zen 3. | |
=== Key changes from {{\\|Zen 2}} === | === Key changes from {{\\|Zen 2}} === | ||
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** Higher [[IPC]] (AMD self-reported +19% IPC) | ** Higher [[IPC]] (AMD self-reported +19% IPC) | ||
** Front-end | ** Front-end | ||
− | + | ** Increased branch prediction bandwidth | |
*** "zero-bubble" branch prediction | *** "zero-bubble" branch prediction | ||
*** L1 BTB doubled from 512 to 1024 entries | *** L1 BTB doubled from 512 to 1024 entries | ||
− | + | ** Improved prefetching | |
− | + | ** Improved µop cache | |
− | + | * Back-end | |
− | + | ** Floating point unit: | |
− | + | *** FMA latency reduced by 1 cycle from 5 to 4. | |
− | + | *** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port. | |
− | + | *** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set. | |
− | + | *** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughput. | |
− | + | *** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation. | |
− | + | ** Integer unit: | |
− | + | *** Integer physical register file increased from 180 to 192 entries | |
− | + | *** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways. | |
− | + | *** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each. | |
− | + | *** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams. | |
− | + | *** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately. | |
− | + | ** Load/store: | |
− | + | *** Load throughput increased from 2 to 3, if not 256b. | |
− | + | *** Store throughput increased from 1 to 2, if not 256b. | |
− | + | *** Store queue increase from 48 to 64 slots. | |
− | + | *** Page table walkers tripled from 2 to 6 for TLB miss handling. | |
{{expand list}} | {{expand list}} | ||
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* {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging | * {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging | ||
** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code> | ** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code> | ||
− | * {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf"/> | + | * {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf">[https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf "Security Analysis of AMD Predictive Store Forwarding"], March 2021</ref> |
− | Sources: <ref name="amd-24593-apm2"/><ref name="amd-24594-apm3"/><ref name="amd-26568-apm4"/> | + | Sources:<ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref><ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref><ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref> |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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** Inclusive of L1 | ** Inclusive of L1 | ||
** ≥ 12 cycles latency | ** ≥ 12 cycles latency | ||
− | ** | + | ** ECC |
* L3 Cache: | * L3 Cache: | ||
− | ** "{{amd|Milan | + | ** "{{amd|Milan|l=core}}": 32 MiB/CCX, up to 256 MiB total |
** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total | ** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total | ||
** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs | ** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs | ||
− | ** Shared by all cores in the | + | ** Shared by all cores in the CCX, configurable<ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref> |
** 16-way set associative | ** 16-way set associative | ||
** 64 B line size | ** 64 B line size | ||
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** Write-back policy | ** Write-back policy | ||
** 46 cycles average load-to-use latency | ** 46 cycles average load-to-use latency | ||
− | ** | + | ** ECC |
** QoS Monitoring and Enforcement V2.0 | ** QoS Monitoring and Enforcement V2.0 | ||
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==== System DRAM ==== | ==== System DRAM ==== | ||
* EPYC 7003 "{{amd|Milan|l=core}}": | * EPYC 7003 "{{amd|Milan|l=core}}": | ||
− | ** 8 channels per socket, up to 16 DIMMs, max. 4 | + | ** 8 channels per socket, up to 16 DIMMs, max. 4 TiB |
− | ** Up to PC4-25600L (DDR4-3200) | + | ** Up to PC4-25600L (DDR4-3200), ECC supported |
− | ** | + | ** SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM, NVDIMM-N |
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* Ryzen 5000 "{{amd|Vermeer|l=core}}": | * Ryzen 5000 "{{amd|Vermeer|l=core}}": | ||
− | ** 2 channels, up to 4 DIMMs, max. 128 | + | ** 2 channels, up to 4 DIMMs, max. 128 GiB |
** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported | ** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported | ||
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* Ryzen 5000 APU "{{amd|Cezanne|l=core}}": | * Ryzen 5000 APU "{{amd|Cezanne|l=core}}": | ||
− | ** | + | ** DDR4-3200 or LPDDR4-4266 |
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− | Sources: <ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h"/><ref name="amd-55898-ppr-1901 | + | Sources:<ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref><ref name="amd-55898-ppr-1901">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref> |
== All Zen 3 Chips == | == All Zen 3 Chips == | ||
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== References == | == References == | ||
− | <references | + | <references/> |
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== See Also == | == See Also == | ||
− | * AMD {{\\|Zen}}, {{\\|Zen 2 | + | * AMD {{\\|Zen}}, {{\\|Zen 2}} |
* Intel {{intel|Tigerlake|l=arch}} | * Intel {{intel|Tigerlake|l=arch}} | ||
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review] | * Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review] | ||
* Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews] | * Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews] |
Facts about "Zen 3 - Microarchitectures - AMD"
codename | Zen 3 + |
core count | 64 +, 56 +, 48 +, 32 +, 28 +, 24 +, 16 +, 12 +, 8 + and 6 + |
designer | AMD + |
first launched | October 8, 2020 + |
full page name | amd/microarchitectures/zen 3 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen 3 + |
pipeline stages | 19 + |