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|manufacturer=GlobalFoundries | |manufacturer=GlobalFoundries | ||
|manufacturer 2=TSMC | |manufacturer 2=TSMC | ||
− | |introduction= | + | |introduction=2019 |
− | |process= | + | |process=14 nm |
− | |process 2= | + | |process 2=7 nm |
− | |process 3 | + | |process 3=12 nm |
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|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
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|extension 27=UMIP | |extension 27=UMIP | ||
|extension 28=CLZERO | |extension 28=CLZERO | ||
− | |core name | + | |core name=Rome |
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|predecessor=Zen+ | |predecessor=Zen+ | ||
|predecessor link=amd/microarchitectures/zen+ | |predecessor link=amd/microarchitectures/zen+ | ||
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|successor link=amd/microarchitectures/zen 3 | |successor link=amd/microarchitectures/zen 3 | ||
}} | }} | ||
− | '''Zen 2''' is [[AMD]]'s successor to {{\\|Zen+}}, and is a [[7 nm process]] [[microarchitecture]] for mainstream mobile, desktops, workstations, and servers. Zen 2 | + | '''Zen 2''' is [[AMD]]'s successor to {{\\|Zen+}}, and is a [[7 nm process]] [[microarchitecture]] for mainstream mobile, desktops, workstations, and servers. Zen 2 will eventually be replaced by {{\\|Zen 3}}. |
For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen 3}}, {{amd|Ryzen 5}}, {{amd|Ryzen 7}}, {{amd|Ryzen 9}}, and {{amd|Ryzen Threadripper}} processors. For servers, Zen is branded as {{amd|EPYC}}. | For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen 3}}, {{amd|Ryzen 5}}, {{amd|Ryzen 7}}, {{amd|Ryzen 9}}, and {{amd|Ryzen Threadripper}} processors. For servers, Zen is branded as {{amd|EPYC}}. | ||
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[[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]] | [[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]] | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
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|- | |- | ||
| {{amd|Renoir|l=core}} || Up to 8/16 || Mainstream APUs with {{\\|Vega}} GPUs | | {{amd|Renoir|l=core}} || Up to 8/16 || Mainstream APUs with {{\\|Vega}} GPUs | ||
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|} | |} | ||
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! colspan="11" | Mainstream | ! colspan="11" | Mainstream | ||
|- | |- | ||
− | | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] | + | | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:amd ryzen 5 logo.png|75px|link=Ryzen 5]] || {{amd|Ryzen 5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk| | + | | [[File:amd ryzen 5 logo.png|75px|link=Ryzen 5]] || {{amd|Ryzen 5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:amd ryzen 7 logo.png|75px|link=Ryzen 7]] || {{amd|Ryzen 7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk| | + | | [[File:amd ryzen 7 logo.png|75px|link=Ryzen 7]] || {{amd|Ryzen 7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:amd ryzen 9 logo.png|75px|link=Ryzen 9]] || {{amd|Ryzen 9}} || High-end Performance || [[12 cores|12]]-[[16 cores|16]] | + | | [[File:amd ryzen 9 logo.png|75px|link=Ryzen 9]] || {{amd|Ryzen 9}} || High-end Performance || [[12 cores|12]]-[[16 cores|16]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
! colspan="10" | Enthusiasts / Workstations | ! colspan="10" | Enthusiasts / Workstations | ||
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! colspan="10" | Embedded / Edge | ! colspan="10" | Embedded / Edge | ||
|- | |- | ||
− | | [[File:epyc embedded logo.png|75px|link=amd/epyc embedded]] || {{amd|EPYC Embedded}} || Embedded / Edge Server Processor || | + | | [[File:epyc embedded logo.png|75px|link=amd/epyc embedded]] || {{amd|EPYC Embedded}} || Embedded / Edge Server Processor || colspan="8" | ? |
|- | |- | ||
− | | [[File:ryzen embedded logo.png|75px|link=amd/ryzen embedded]] || {{amd|Ryzen Embedded}} || Embedded APUs || | + | | [[File:ryzen embedded logo.png|75px|link=amd/ryzen embedded]] || {{amd|Ryzen Embedded}} || Embedded APUs || colspan="8" | ? |
|} | |} | ||
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== Process technology == | == Process technology == | ||
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− | + | === Key changes from {{\\|Zen+}} === | |
* [[7 nm process]] (from [[12 nm]]) | * [[7 nm process]] (from [[12 nm]]) | ||
** I/O die utilizes [[12 nm]] | ** I/O die utilizes [[12 nm]] | ||
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Furthermore, the User-Mode Instruction Prevention ({{x86|UMIP}}) extension. | Furthermore, the User-Mode Instruction Prevention ({{x86|UMIP}}) extension. | ||
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=== Block Diagram === | === Block Diagram === | ||
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==== Branch Prediction Unit ==== | ==== Branch Prediction Unit ==== | ||
− | The branch prediction unit guides instruction fetching and attempts to predict branches and their target to avoid pipeline stalls or the pursuit of incorrect execution paths. The Zen 2 BPU almost doubles the branch target buffer capacity, doubles the size of the indirect target array, and introduces a TAGE predictor. According to AMD it exhibits a 30% lower misprediction rate than its | + | The branch prediction unit guides instruction fetching and attempts to predict branches and their target to avoid pipeline stalls or the pursuit of incorrect execution paths. The Zen 2 BPU almost doubles the branch target buffer capacity, doubles the size of the indirect target array, and introduces a TAGE predictor. According to AMD it exhibits a 30% lower misprediction rate than its counterpart in the {{\\|Zen}}/{{\\|Zen+}} microarchitecture. |
Once per cycle the next address logic determines if branch instructions have been identified in the current 64-byte instruction fetch block, and if so, consults several branch prediction facilities about the most likely target and calculates a new fetch block address. If no branches are expected it calculates the address of the next sequential block. Branches are evaluated much later in the integer execution unit which provides the actual branch outcome to redirect instruction fetching and refine the predictions. The dispatch unit can also cause redirects to handle mispredictions and exceptions. | Once per cycle the next address logic determines if branch instructions have been identified in the current 64-byte instruction fetch block, and if so, consults several branch prediction facilities about the most likely target and calculates a new fetch block address. If no branches are expected it calculates the address of the next sequential block. Branches are evaluated much later in the integer execution unit which provides the actual branch outcome to redirect instruction fetching and refine the predictions. The dispatch unit can also cause redirects to handle mispredictions and exceptions. | ||
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== Die == | == Die == | ||
− | === | + | === Core Complex Die === |
− | + | There are 4 cores per CCX and 2 CCXs per CCD. | |
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− | + | * CCD: 74 mm² (AMD) | |
− | + | * CCX: 31.3 mm² (AMD) | |
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− | * | ||
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− | * CCX | ||
* 2 × 16 MiB L3 cache: 2 × 16.8 mm² (estimated) | * 2 × 16 MiB L3 cache: 2 × 16.8 mm² (estimated) | ||
+ | * Zen 2 core incl. 512 KiB L2 cache: 3.64 mm² (estimated) | ||
+ | |||
:[[File:AMD_Zen_2_CCD.jpg|500px]] | :[[File:AMD_Zen_2_CCD.jpg|500px]] | ||
− | === | + | === Renoir === |
− | * | + | * [[N7|7-nanometer process]] |
− | * | + | * 13 metal layers |
− | * | + | * 9,800,000,000 transistors |
− | + | * 156 mm² die size | |
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:[[File:renoir die.png|500px]] | :[[File:renoir die.png|500px]] | ||
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== All Zen 2 Chips == | == All Zen 2 Chips == | ||
− | <!-- NOTE: | + | <!-- NOTE: |
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
If a microprocessor is missing from the list, an appropriate article for it needs to be | If a microprocessor is missing from the list, an appropriate article for it needs to be | ||
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== Designers == | == Designers == | ||
− | * David Suggs, | + | * David Suggs, chief architect |
− | |||
== Bibliography == | == Bibliography == | ||
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* AMD 'Next Horizon', November 6, 2018 | * AMD 'Next Horizon', November 6, 2018 | ||
* AMD. Lisa Su ''Keynote''. May 26, 2019 | * AMD. Lisa Su ''Keynote''. May 26, 2019 | ||
− | + | * AMD 'Next Horizon Gaming' event at E3, June 10, 2019 | |
− | |||
== See Also == | == See Also == | ||
* Intel {{intel|Ice Lake|l=arch}} | * Intel {{intel|Ice Lake|l=arch}} |
Facts about "Zen 2 - Microarchitectures - AMD"
codename | Zen 2 + |
core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 64 + |
designer | AMD + |
first launched | July 2019 + |
full page name | amd/microarchitectures/zen 2 + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen 2 + |
pipeline stages | 19 + |