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− | {{amd title|Infinity Fabric (IF)}} | + | {{amd title|Infinity Fabric (IF)}}[[File:amd infinity fabric.svg|right|250px]] |
− | '''Infinity Fabric''' ('''IF''') is a | + | '''Infinity Fabric''' ('''IF''') is a system [[interconnect architecture]] that facilitates data and control transmission accross all linked components. This architecture is utilized by [[AMD]]'s recent microarchitectures for both CPU (i.e., {{amd|Zen|l=arch}}) and graphics (e.g., {{amd|Vega|l=arch}}), and any other additional accelerators they might add in the future. The fabric was first announced and detailed in April 2017 by Mark Papermaster, AMD's SVP and CTO. |
== Overview == | == Overview == | ||
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The Infinity Fabric consists of two separate communication planes - Infinity '''Scalable Data Fabric''' ('''SDF''') and the Infinity '''Scalable Control Fabric''' ('''SCF'''). The SDF is the primary means by which data flows around the system between endpoints (e.g. [[NUMA node]]s, [[PHY]]s). The SDF might have dozens of connecting points hooking together things such as [[PCIe]] PHYs, [[memory controller]]s, USB hub, and the various computing and execution units. The SDF is a [[superset]] of what was previously [[HyperTransport]]. The SCF is a complementary plane that handles the transmission of the many miscellaneous system control signals - this includes things such as thermal and power management, tests, security, and 3rd party IP. With those two planes, AMD can efficiently scale up many of the basic computing blocks. | The Infinity Fabric consists of two separate communication planes - Infinity '''Scalable Data Fabric''' ('''SDF''') and the Infinity '''Scalable Control Fabric''' ('''SCF'''). The SDF is the primary means by which data flows around the system between endpoints (e.g. [[NUMA node]]s, [[PHY]]s). The SDF might have dozens of connecting points hooking together things such as [[PCIe]] PHYs, [[memory controller]]s, USB hub, and the various computing and execution units. The SDF is a [[superset]] of what was previously [[HyperTransport]]. The SCF is a complementary plane that handles the transmission of the many miscellaneous system control signals - this includes things such as thermal and power management, tests, security, and 3rd party IP. With those two planes, AMD can efficiently scale up many of the basic computing blocks. | ||
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== Scalable Data Fabric (SDF) == | == Scalable Data Fabric (SDF) == | ||
[[File:amd zeppelin sdf plane block.svg|class=wikichip_ogimage|400px|right]] | [[File:amd zeppelin sdf plane block.svg|class=wikichip_ogimage|400px|right]] | ||
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=== SerDes === | === SerDes === | ||
[[File:amd if-ifop-serdes.png|right|thumb|IFOP SerDes]] | [[File:amd if-ifop-serdes.png|right|thumb|IFOP SerDes]] | ||
− | The Infinity Scalable Data Fabric (SDF) | + | The Infinity Scalable Data Fabric (SDF) employees two different types of [[SerDes]] links - '''Infinity Fabric On-Package''' ('''IFOP''') and '''Infinity Fabric InterSocket''' ('''IFIS'''). |
==== IFOP ==== | ==== IFOP ==== | ||
− | The '''Infinity Fabric On-Package''' ('''IFOP''') SerDes deal with die-to- | + | The '''Infinity Fabric On-Package''' ('''IFOP''') SerDes deal with die-to-do communication in the same package. AMD designed a fairly straightforward custom SerDes suitable for short-in package trace lengths which can achieve a power efficiency of roughly 2 pJ/b. This was done by using a 32-bit low-swing [[single-ended]] data transmission with differential clocking which consumed roughly half the power of an equivalent differential drive. They utilize a zero-power driver state from the TX/RX impedance termination to the ground while the driver pull-up is disabled. This allows transmitting zeros with less power than transmitting ones which of was also leveraged for when the link was idle. Additionally, [[inversion encoding]] was also used in order to save another 10% average power per bit. |
− | Due to the performance sensitivity of the on-package links, the IFOP links are over-provisioned by about a factor of two relative to DDR4 channel bandwidth for mixed read/write traffic. | + | Due to the performance sensitivity of the on-package links, the IFOP links are over-provisioned by about a factor of two relative to DDR4 channel bandwidth for mixed read/write traffic. This a bidirectional link and CRC is transmitted along with every cycle of data. The IFOP SerDes do four transfers per CAKE clock. |
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− | Since the CAKEs operate at the same frequency as the DRAM's MEMCLK frequency, the bandwidth is fully dependent on that. For a system using DDR4-2666 DIMMs, this means the CAKEs will be operating at 1333.33 MHz meaning the IFOPs will have a bi-directional bandwidth of 42.667 GB/s | + | Since the CAKEs operate at the same frequency as the DRAM's MEMCLK frequency, the bandwidth is fully dependent on that. For a system using DDR4-2666 DIMMs, this means the CAKEs will be operating at 1333.33 MHz meaning the IFOPs will have a bi-directional bandwidth of 42.667 GB/s. |
==== IFIS ==== | ==== IFIS ==== | ||
− | '''Infinity Fabric InterSocket''' ('''IFIS''') SerDes are the second type which are used for package-to-package communications such as in two-way [[multiprocessing]]. The IFIS were designed so they could [[multiplexed]] with other protocols such as [[PCIe]] and [[SATA]]. They operate on TX/RX 16 | + | '''Infinity Fabric InterSocket''' ('''IFIS''') SerDes are the second type which are used for package-to-package communications such as in two-way [[multiprocessing]]. The IFIS were designed so they could [[multiplexed]] with other protocols such as [[PCIe]] and [[SATA]]. They operate on TX/RX 16 differential data lanes at roughly 11 pJ/b (by the way, those links are aligned with the package pinout of standard PCIe lanes). Because they are 16-bit wide they run at 8 transfers per CAKE clock. Compared to the IFOP, the IFIS links have 8/9 of the bandwidth. |
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− | For a system using DDR4-2666 DIMMs, the CAKEs will be operating at 1333.33 | + | For a system using DDR4-2666 DIMMs, the CAKEs will be operating at 1333.33 Mz meaning the IFIS will have a bidirectional bandwidth of 37.926 GB/s. |
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− | + | == Scalable Control Fabric (SDF) == | |
− | + | The Infinity Scalable Control Fabric (SCF) is the control communication plane of the Infinity Fabric. | |
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== References == | == References == | ||
* AMD Infinity Fabric introduction by Mark Papermaster, April 6, 2017 | * AMD Infinity Fabric introduction by Mark Papermaster, April 6, 2017 | ||
* AMD EPYC Tech Day, June 20, 2017 | * AMD EPYC Tech Day, June 20, 2017 | ||
− | * | + | * ISSCC 2018 |
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