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The "Milan" I/O die has largely the same features as the prior generation die fabricated on [[GlobalFoundries]]' [[14_nm_lithography_process|14 nanometer "14LPP" process]]. <!-- AMD did not disclose manufacturing details about the "Milan" sIOD. A diagram in Publ. #57091 "HPC Tuning for EPYC 7003" labels the die as "14nm". --> Apart of the memory controllers and I/O facilites described below it integrates an {{amd|secure processor|AMD Secure Processor}}, a <abbr title="System Management Unit">SMU</abbr>, <abbr title="Real Time Clock">RTC</abbr>, and other functions traditionally found in a separate chipset. | The "Milan" I/O die has largely the same features as the prior generation die fabricated on [[GlobalFoundries]]' [[14_nm_lithography_process|14 nanometer "14LPP" process]]. <!-- AMD did not disclose manufacturing details about the "Milan" sIOD. A diagram in Publ. #57091 "HPC Tuning for EPYC 7003" labels the die as "14nm". --> Apart of the memory controllers and I/O facilites described below it integrates an {{amd|secure processor|AMD Secure Processor}}, a <abbr title="System Management Unit">SMU</abbr>, <abbr title="Real Time Clock">RTC</abbr>, and other functions traditionally found in a separate chipset. | ||
| − | In an interview on March 15, 2021 AMD SVP Forrest Norrod confirmed plans for another server processor series based on the Zen 3 microarchitecture with the codename "Trento". These processors will use a different I/O die with additional coherent {{amd|Infinity Fabric}} links to attach accelerators. They will be used in the exaflop [[wikipedia:Frontier_%28supercomputer%29|Frontier]] supercomputer with nodes comprising one EPYC CPU and four Radeon Instinct MI200 GPUs.<ref>"[https://www.anandtech.com/show/16548/interview-with-amd-forrest-norrod-milan The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod]. anandtech.com. Retrieved May 2021.</ref> "Milan" processors will power the 100 petaflop [[wikipedia:Perlmutter_%28supercomputer%29|Perlmutter]] supercomputer, [https://news.iu.edu/stories/2020/06/iub/releases/01-jetstream-cloud-computing-awarded-nsf-grant.html Jetstream 2] | + | In an interview on March 15, 2021 AMD SVP Forrest Norrod confirmed plans for another server processor series based on the Zen 3 microarchitecture with the codename "Trento". These processors will use a different I/O die with additional coherent {{amd|Infinity Fabric}} links to attach accelerators. They will be used in the exaflop [[wikipedia:Frontier_%28supercomputer%29|Frontier]] supercomputer with nodes comprising one EPYC CPU and four Radeon Instinct MI200 GPUs.<ref>"[https://www.anandtech.com/show/16548/interview-with-amd-forrest-norrod-milan The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod]. anandtech.com. Retrieved May 2021.</ref> "Milan" processors will power the 100 petaflop [[wikipedia:Perlmutter_%28supercomputer%29|Perlmutter]] supercomputer, [https://news.iu.edu/stories/2020/06/iub/releases/01-jetstream-cloud-computing-awarded-nsf-grant.html Jetstream 2] and [https://www.rcac.purdue.edu/compute/anvil/ Anvil]. |
=== Memory Interface === | === Memory Interface === | ||
| − | The "Milan" I/O die integrates eight [[wikipedia:DDR4 SDRAM|DDR4]] memory controllers (<abbr title="Unified Memory Controller">UMC</abbr>s), two per I/O die quadrant, which achieve data rates from 1333 to 3200 MT/s.<ref name="amd-55898">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref> Up to 2 DIMMs per channel are supported. The {{amd|Infinity Fabric}} and memory bus clock can be coupled to | + | The "Milan" I/O die integrates eight [[wikipedia:DDR4 SDRAM|DDR4]] memory controllers (<abbr title="Unified Memory Controller">UMC</abbr>s), two per I/O die quadrant, which achieve data rates from 1333 to 3200 MT/s.<ref name="amd-55898">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref> Up to 2 DIMMs per channel are supported, the maximum data rate of 2DPC configurations is 2933 MT/s.<ref name="amd-56873">{{cite techdoc|title=Memory Population Guidelines for AMD EPYC™ 7003 Series Processors|publ=AMD|pid=56873|rev=0.70|date=2020-11}}</ref> The {{amd|Infinity Fabric}} and memory bus clock can be coupled to reduce the memory latency, "Milan" processors permit this up to 1600 MHz matching DDR4-3200 memory.<ref name="amd-57091">{{cite techdoc|title=High Performance Computing (HPC) Tuning Guide for AMD EPYC™ 7003 Series Processors|url=https://www.amd.com/system/files/documents/high-performance-computing-tuning-guide-amd-epyc7003-series-processors.pdf|publ=AMD|pid=57091|rev=2.0|date=2021-03}}</ref> The memory controllers support [[wikipedia:ECC memory|ECC memory]] and the following DIMM types:<ref name="amd-56873"/> |
* <abbr title="Single Rank">SR</abbr>/<abbr title="Dual Rank">DR</abbr> [[wikipedia:Registered memory|RDIMM]] built with x4 and x8 DDR4 devices | * <abbr title="Single Rank">SR</abbr>/<abbr title="Dual Rank">DR</abbr> [[wikipedia:Registered memory|RDIMM]] built with x4 and x8 DDR4 devices | ||
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The maximum total memory capacity is 4 TiB per socket using 16 LRDIMMs or 3DS DIMMs of 256 GiB capacity. | The maximum total memory capacity is 4 TiB per socket using 16 LRDIMMs or 3DS DIMMs of 256 GiB capacity. | ||
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The memory channels are designated A to H. "Rome" and "Milan" processors support 2-, 4-, 8-, and 16-way (on 2P systems) memory interleaving. 4-way mode interleaves the memory channels ABCD and/or EFGH, or CDGH if only these four channels are populated. In contrast to the prior generation CDGH interleaving is supported by all EPYC 7003 <abbr title="Stock Keeping Unit">SKU</abbr>s with 128 MiB L3 cache or less, none having only two <abbr title="Core Complex Die">CCD</abbr>s. Additionally all "Milan" processors support 6-way interleaving if channels B and F remain unpopulated, with a maximum of 256 GiB capacity per channel and restricted to 2 or 4 KiB interleaving size.<ref name="amd-56873"/> The new options enable balanced memory utilization at reduced memory cost when peak memory performance is not required. | The memory channels are designated A to H. "Rome" and "Milan" processors support 2-, 4-, 8-, and 16-way (on 2P systems) memory interleaving. 4-way mode interleaves the memory channels ABCD and/or EFGH, or CDGH if only these four channels are populated. In contrast to the prior generation CDGH interleaving is supported by all EPYC 7003 <abbr title="Stock Keeping Unit">SKU</abbr>s with 128 MiB L3 cache or less, none having only two <abbr title="Core Complex Die">CCD</abbr>s. Additionally all "Milan" processors support 6-way interleaving if channels B and F remain unpopulated, with a maximum of 256 GiB capacity per channel and restricted to 2 or 4 KiB interleaving size.<ref name="amd-56873"/> The new options enable balanced memory utilization at reduced memory cost when peak memory performance is not required. | ||
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=== Input/Output Interfaces === | === Input/Output Interfaces === | ||
| − | The "Milan" I/O die integrates eight 16-lane [[wikipedia:PCI Express|PCIe]] Gen 4 (16 GT/s) controllers. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links. Each controller supports up to eight PCIe links. On dual-socket systems four, or optionally three, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these <abbr title="External Global Memory Interconnect, 2nd generation">xGMI-2</abbr> links can reach 18 GT/s. The I/O die also integrates four [[wikipedia:Serial ATA|SATA]] 3.0 (6 Gb/s) controllers which support up to eight links each, multiplexed with the lower eight lanes of four x16 links. [[wikipedia:NVM Express|NVMe]] devices are supported as well. An additional 2-lane PCIe Gen 2 controller powers the WAFL links. One or both of these lanes serve as {{amd|Infinity Fabric#Scalable Control Fabric | + | The "Milan" I/O die integrates eight 16-lane [[wikipedia:PCI Express|PCIe]] Gen 4 (16 GT/s) controllers. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links. Each controller supports up to eight PCIe links. On dual-socket systems four, or optionally three, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these <abbr title="External Global Memory Interconnect, 2nd generation">xGMI-2</abbr> links can reach 18 GT/s. The I/O die also integrates four [[wikipedia:Serial ATA|SATA]] 3.0 (6 Gb/s) controllers which support up to eight links each, multiplexed with the lower eight lanes of four x16 links. [[wikipedia:NVM Express|NVMe]] devices are supported as well. An additional 2-lane PCIe Gen 2 controller powers the WAFL links. One or both of these lanes serve as {{amd|Infinity Fabric#Scalable Control Fabric|SCF}} links between sockets and are otherwise available for I/O, e.g. to attach a [[wikipedia:Intelligent Platform Management Interface#Baseboard management controller|BMC]]. In sum up to 128 + 2 PCIe lanes are available per socket and up to 2 × 80 + 2 × 1 = 162 lanes total on dual-socket platforms.<ref name="amd-55898"/> |
With the "Milan" series the integrated <abbr title="Input/Output Memory Management Unit">IOMMU</abbr>s were optimized to better handle high-bandwidth devices such as 200 Gbps Ethernet adapters. Support for hotplug surprise removal was brought up to current [[wikipedia:PCI-SIG|PCI-SIG]] implementation guidelines. | With the "Milan" series the integrated <abbr title="Input/Output Memory Management Unit">IOMMU</abbr>s were optimized to better handle high-bandwidth devices such as 200 Gbps Ethernet adapters. Support for hotplug surprise removal was brought up to current [[wikipedia:PCI-SIG|PCI-SIG]] implementation guidelines. | ||
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* TDP range 155 to 280 Watt, configurable | * TDP range 155 to 280 Watt, configurable | ||
| − | == | + | == Milan Processors == |
| + | |||
{{chip identification | {{chip identification | ||
| − | + | | parts = 7 | |
| − | | parts = | + | | ex 1 = EPYC |
| − | | ex 1 = EPYC | + | | ex 2 = |
| − | | ex 2 = | + | | ex 3 = 7 |
| − | | ex 3 = | ||
| ex 4 = 5 | | ex 4 = 5 | ||
| − | | ex 5 = 3 | + | | ex 5 = 5 |
| − | | ex | + | | ex 6 = 3 |
| + | | ex 7 = P | ||
| desc 1 = '''Product Family''' | | desc 1 = '''Product Family''' | ||
| − | | desc | + | | desc 3 = <table style="text-align:left"><th colspan="2">Product Series</th> |
<tr><th>7xxx</th><td>High-performance server CPU/SOC</td></tr></table> | <tr><th>7xxx</th><td>High-performance server CPU/SOC</td></tr></table> | ||
| − | | desc | + | | desc 4 = <table style="text-align:left"> |
<th colspan="2">Product Model (Core Count)</th> | <th colspan="2">Product Model (Core Count)</th> | ||
<tr><th>2</th><td>8 cores</td></tr> | <tr><th>2</th><td>8 cores</td></tr> | ||
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<tr><th>6</th><td>40-56</td></tr> | <tr><th>6</th><td>40-56</td></tr> | ||
<tr><th>7</th><td>64 cores</td></tr></table> | <tr><th>7</th><td>64 cores</td></tr></table> | ||
| − | | desc | + | | desc 5 = <table style="text-align:left"> |
<th colspan="2">Performance Level</th> | <th colspan="2">Performance Level</th> | ||
<tr><th>1</th><td>Value</td></tr> | <tr><th>1</th><td>Value</td></tr> | ||
<tr><th>4, 5, 6</th><td>Performance</td></tr> | <tr><th>4, 5, 6</th><td>Performance</td></tr> | ||
<tr><th>F</th><td>Frequency optimized and high cache/core ratio,<br/>high performance per core</td></tr></table> | <tr><th>F</th><td>Frequency optimized and high cache/core ratio,<br/>high performance per core</td></tr></table> | ||
| − | | desc | + | | desc 6 = <table style="text-align:left"> |
<th colspan="2">Generation</th> | <th colspan="2">Generation</th> | ||
<tr><th>3</th><td>Third generation, 7003 "Milan" series</td></tr></table> | <tr><th>3</th><td>Third generation, 7003 "Milan" series</td></tr></table> | ||
| − | | desc | + | | desc 7 = <table style="text-align:left"> |
<th colspan="2">Feature Modifier</th> | <th colspan="2">Feature Modifier</th> | ||
<tr><th>(none)</th><td>1P, 2P</td></tr> | <tr><th>(none)</th><td>1P, 2P</td></tr> | ||
<tr><th>P</th><td>1P (single socket) only</td></tr></table> | <tr><th>P</th><td>1P (single socket) only</td></tr></table> | ||
}} | }} | ||
| + | <br/> | ||
| − | |||
<!-- NOTE: | <!-- NOTE: | ||
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
Facts about "Milan - Cores - AMD"
| designer | AMD + |
| first announced | January 12, 2021 + |
| first launched | March 15, 2021 + |
| instance of | core + |
| isa | x86-64 + |
| manufacturer | TSMC + and GlobalFoundries + |
| microarchitecture | Zen 3 + |
| name | Milan + |
| package | FCLGA-4094 + and SP3 + |
| socket | LGA-4094 + and SP3 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |