Editing alchemy/au1550-400mbd

{{title|Alchemy Au1550-400MBD}}
{{chip
|name=Alchemy Au1550-400MBD
|no image=Yes
|designer=AMD
|model number=Au1550-400MBD
|part number=Au1550-400MBDAA
|market=Embedded
|first announced=February 24, 2004
|first launched=May 2004
|last order=
|last shipment=
|release price (tray)=$26.57
|family=Alchemy
|frequency=400 MHz
|isa=MIPS32
|microarch=Au1
|platform=
|chipset=
|core stepping=AA
|manufacturer=
|process=
|transistors=
|technology=CMOS
|die area=
|word size=32 bit
|core count=1
|max cpus=1
|max memory=192 MiB
|v core=1.2 V
|v core tolerance=10%
|v io=3.3 V
|tdp=1460 mW
|tdp typical=500 mW
|tcase min=0 °C
|tcase max=85 °C
|tstorage min=-40 °C
|tstorage max=125 °C
}}
'''Au1550-400MBD''' was a {{arch|32}} ultra low power embedded microprocessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[AMD]] based on {{alchemy|alchemy|earlier}} [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typical {{abbr|TDP}} of 500 mW and maximum TDP of 1460 mW. It is the Pb-free version of the {{\\|Au1550-400MBC}}.

== Cache ==
{{main|alchemy/microarchitectures/au1#Memory_Hierarchy|l1=Au1 § Cache}}
{{cache size
|l1 cache=32 KiB
|l1i cache=16 KiB
|l1i break=1 × 16 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=1 × 16 KiB
|l1d desc=4-way set associative
|l1d policy=write-back
}}

== Memory controller ==
Au1550 processors integrate two independent memory controllers, an SDRAM controller which supports 3.3&nbsp;V and 2.5&nbsp;V SDR devices and 2.5&nbsp;V DDR devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. 

{{memory controller
|type=SDR-166
|type 2=DDR-400
|ecc=No
|controllers=1
|channels=1
|max mem=192 MiB
|width=16 bit
|width 2=32 bit
|max bandwidth=1.600 GB/s
}}

== Expansions ==
* PCI 2.2 controller, 32-bit bus, 33 or 66&nbsp;MHz
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller with OTG support
** Two USB host ports and one device port (co-opting a host port in OTG mode)
* Two 10/100 Mbit/s Ethernet MAC controllers
* Four Programmable Serial Controllers supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols
* Three {{abbr|UART}}s
* Up to 43 {{abbr|GPIO}}s

== Graphics ==
This processor has no integrated graphics processing unit.

== Features ==
* 16-channel descriptor-based DMA controller
** Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
** 36-bit source and destination addresses with no alignment requirement
** Scatter/gather and stride transfers
** Compare and branch descriptors
* SafeNet Security Engine to accelerate IP packet encryption/decryption in hardware
** DES, 3DES, AES, ARC4 encryption algorithms
** MD5, SHA1 hash algorithms
** Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets
** Supports a two-pass hash-then-encrypt implementation of the SSL protocol using either MD5 or SHA1 and 3DES or ARC4 ciphers
** True entropy-based random number generator
* {{abbr|RTC}} and {{abbr|TOY|Time Of Year}} timer
* Two interrupt controllers
* Power management unit
* MIPS EJTAG interface
* Idle, Sleep, Hibernate Mode

== Package ==
* 483-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
* 25 × 25 grid, 0.8&nbsp;mm pitch
* 21&nbsp;mm × 21&nbsp;mm × 1.7&nbsp;mm

== Bibliography ==
* {{cite techdoc|title=Product Brief: AMD Alchemy™ Au1550™ Processor Security Network Processor|url=https://web.archive.org/web/20061015230936id_/http://www.razamicroelectronics.com/pub_assets/31195c_pcsau1550prodbrief.pdf|publ=AMD|pid=31195|rev=C|date=2004}}
* {{cite techdoc|title=AMD Alchemy™ Au1550™ Security Network Processor Data Book|url=https://web.archive.org/web/20060708150440id_/http://www.amd.com:80/files/connectivitysolutions/aufamily/au1550/30283D_Au1550_db.pdf|publ=AMD|pid=30283|rev=D|date=2006-05}}
base frequency	400 MHz (0.4 GHz, 400,000 kHz) +
core count	1 +
core stepping	AA +
core voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
core voltage tolerance	10% +
designer	AMD +
family	Alchemy +
first announced	February 24, 2004 +
first launched	May 2004 +
full page name	alchemy/au1550-400mbd +
has ecc memory support	false +
instance of	microprocessor +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	MIPS32 +
l1$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description	4-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
ldate	May 2004 +
market segment	Embedded +
max case temperature	358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count	1 +
max memory	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth	1.49 GiB/s (1,525.879 MiB/s, 1.6 GB/s, 1,600 MB/s, 0.00146 TiB/s, 0.0016 TB/s) +
max memory channels	1 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Au1 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Au1550-400MBD +
name	Alchemy Au1550-400MBD +
part number	Au1550-400MBDAA +
release price	$ 26.57 (€ 23.91, £ 21.52, ¥ 2,745.48) +
release price (tray)	$ 26.57 (€ 23.91, £ 21.52, ¥ 2,745.48) +
smp max ways	1 +
supported memory type	SDR-166 + and DDR-400 +
tdp	1.46 W (1,460 mW, 0.00196 hp, 0.00146 kW) +
tdp (typical)	0.5 W (500 mW, 6.705e-4 hp, 5.0e-4 kW) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +