Editing alchemy/au1250-400mgd

{{title|Alchemy Au1250-400MGD}}
{{chip
|name=Alchemy Au1250-400MGD
|no image=Yes
|designer=RMI
|model number=Au1250-400MGD
|part number=Au1250-400MGD
|market=Embedded
|first announced=January 9, 2007
|first launched=June 5, 2007
|last order=
|last shipment=
|release price (tray)=
|family=Alchemy
|frequency=400 MHz
|isa=MIPS32
|microarch=Au1
|platform=
|chipset=
|manufacturer=
|process=
|transistors=
|technology=CMOS
|die area=
|word size=32 bit
|core count=1
|max cpus=1
|max memory=512 MiB
|v core=1.2 V
|v core tolerance=10%
|v io=3.3 V
|tdp=1200 mW
|tdp typical=560 mW
|tcase min=0 °C
|tcase max=70 °C
|tstorage min=-40 °C
|tstorage max=125 °C
}}
'''Au1250-400MGD''' was a {{arch|32}} ultra low power embedded microprocessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 400 MHz with a typical {{abbr|TDP}} of 560 mW and maximum TDP of 1200 mW. It was also available with an industrial temperature range as {{\\|Au1250-400MGF}}.

== Cache ==
{{main|alchemy/microarchitectures/au1#Memory_Hierarchy|l1=Au1 § Cache}}
{{cache size
|l1 cache=32 KiB
|l1i cache=16 KiB
|l1i break=1 × 16 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=1 × 16 KiB
|l1d desc=4-way set associative
|l1d policy=write-back
}}

== Memory controller ==
Au1250 processors integrate two independent memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode, and other I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. The integrated LCD and MAE peripherals can access the SDRAM controller through a 64-bit side bus running at the SBUS frequency. 

{{memory controller
|type=DDR-400
|type 2=DDR2-533
|ecc=No
|controllers=1
|channels=1
|max mem=512 MiB
|width=16 bit
|width 2=32 bit
|max bandwidth=1.600 GB/s
}}

== Expansions ==
* USB 2.0 ({{abbr|EHCI}}) and 1.1 ({{abbr|OHCI}}) host controller, USB 2.0 device controller with OTG support
** One USB host port and one host/device port, each low/fast/high speed capable
* Two [[wikipedia:SD card|Secure Digital]]/{{abbr|SDHC}}/{{abbr|SDIO}}/{{abbr|MMC}} 1.1 controllers
* Two Programmable Serial Controllers supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols
* Two {{abbr|UART}}s
* Up to 48 {{abbr|GPIO}}s

== Graphics ==
This processor integrates an LCD controller for panels with a resolution up to 2048 × 2048 pixels.
* TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
* STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
* Frame buffer formats:
** 1/2/4/8-bpp pass through/grayscale/palettized
** 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0
** 24-bpp 8:8:8:0
** 32-bpp 8:8:8:8 RGBA
* Four overlay windows with double buffering
* Gamma correction, alpha blending, and chroma keying
* 32 × 32 × 2 bpp hardware cursor

== Features ==
* Camera Interface Module (CIM)
** [[wikipedia:ITU-R BT.656|ITU-R BT.656]] compatible 8/9/10-bit bus running at up to 33 MHz
** Support for UYVY and Bayer RGB to planar format conversion
* Media Acceleration Engine (MAE) to accelerate video decoding in hardware
** Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1
** Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters
** Hardware colorspace conversion and scaling with 4-tap filter, also for CIM
** Video decode resolution up to D1 720 × 480 NTSC / 720 × 576 PAL
* 16-channel descriptor-based DMA controller
** Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
** 36-bit source and destination addresses with no alignment requirement
** Scatter/gather and stride transfers
** Compare and branch descriptors
* AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes
* {{abbr|RTC}} and {{abbr|TOY|Time Of Year}} timer
* Two interrupt controllers
* Power management unit
* MIPS EJTAG interface
* Idle, Sleep, Hibernate Mode

== Package ==
* 372-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
* 23 × 23 grid, 0.8&nbsp;mm pitch
* 19&nbsp;mm × 19&nbsp;mm × 1.4&nbsp;mm

== Bibliography ==
* {{cite techdoc|title=RMI Alchemy™ Au1210™ Navigation Processor and Au1250™ Media Processor Data Book|file=RMI-Au1210-Au1250-DB.pdf|publ=RMI Corp.|rev=A|date=2007-04}}
base frequency	400 MHz (0.4 GHz, 400,000 kHz) +
core count	1 +
core voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
core voltage tolerance	10% +
designer	RMI +
family	Alchemy +
first announced	January 9, 2007 +
first launched	June 5, 2007 +
full page name	alchemy/au1250-400mgd +
has ecc memory support	false +
instance of	microprocessor +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	MIPS32 +
l1$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description	4-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
ldate	June 5, 2007 +
market segment	Embedded +
max case temperature	343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count	1 +
max memory	512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB, 4.882812e-4 TiB) +
max memory bandwidth	1.49 GiB/s (1,525.879 MiB/s, 1.6 GB/s, 1,600 MB/s, 0.00146 TiB/s, 0.0016 TB/s) +
max memory channels	1 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Au1 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Au1250-400MGD +
name	Alchemy Au1250-400MGD +
part number	Au1250-400MGD +
smp max ways	1 +
supported memory type	DDR-400 + and DDR2-533 +
tdp	1.2 W (1,200 mW, 0.00161 hp, 0.0012 kW) +
tdp (typical)	0.56 W (560 mW, 7.5096e-4 hp, 5.6e-4 kW) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +