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We have a diagram of how the {{amd|Zen#Modules (Zeppelin)|Zeppelin|l=arch}} can be configured. In particular, you can only have x48 lanes dedicated to the GPU. Those lanes come from 2 * [dies] with each die having x16 + x8 configuration dedicated to graphics/acceleration for a total of 2 * (x16+x8) = 48 lanes. Each die also delivers 2 * [dies] = 2 * (x4+x4) = x16 additional lanes. AMD steals x4 permanently for the chipset, so you're left with just x12 (x4+x4+x4) for I/O. When I last talked with AMD I was told those can actually not be combined with the other 48 lanes for high-bandwidth 60 lanes, they are effectively limited to SATA/M.2. I can try to contact AMD again to get more clarification about this. --[[User:David|David]] ([[User talk:David|talk]]) 14:38, 4 September 2017 (EDT) | We have a diagram of how the {{amd|Zen#Modules (Zeppelin)|Zeppelin|l=arch}} can be configured. In particular, you can only have x48 lanes dedicated to the GPU. Those lanes come from 2 * [dies] with each die having x16 + x8 configuration dedicated to graphics/acceleration for a total of 2 * (x16+x8) = 48 lanes. Each die also delivers 2 * [dies] = 2 * (x4+x4) = x16 additional lanes. AMD steals x4 permanently for the chipset, so you're left with just x12 (x4+x4+x4) for I/O. When I last talked with AMD I was told those can actually not be combined with the other 48 lanes for high-bandwidth 60 lanes, they are effectively limited to SATA/M.2. I can try to contact AMD again to get more clarification about this. --[[User:David|David]] ([[User talk:David|talk]]) 14:38, 4 September 2017 (EDT) | ||
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