View source for Module:node

local node = {}
local origArgs

function has_arg(name)
	-- The argument can exist and be empty or not exist at all
	return string.len(origArgs[name] or '') > 0
end

function arg(name)
	return origArgs[name]
end

function node.node(frame)
    if frame == mw.getCurrentFrame() then
        origArgs = frame:getParent().args
    else
        origArgs = frame.args
    end

    if arg('node') == '5 nm' then
    	return '' ..
'<table class="wikitable" style="text-align: center;">' ..
'<tr><th colspan="2">&nbsp;</th><th colspan="2">[[Intel]]</th><th colspan="2">[[TSMC]]</th><th colspan="2">[[Samsung]]</th></tr>' ..
'<tr><th colspan="2">Process</th><td colspan="2">P1278 (CPU), P1279 (SoC)</td><td colspan="2">N5, N5P</td><td colspan="2">5LPP</td></tr>' ..
'<tr><th colspan="2">Production</th><td colspan="2">2023</td><td colspan="2">Q1\'2020</td><td colspan="2">2020</td></tr>' ..
'<tr><th rowspan="2">Litho</th><th>Lithography</th><td colspan="6">[[EUV]]</td></tr>' ..
'<tr><th>Immersion<br>Exposure</th><td colspan="2"></td><td colspan="2">SE (EUV)<br>DP (193i)</td><td colspan="2">SE (EUV)<br>DP (193i)</td></tr>' ..
'<tr><th rowspan="2">[[Wafer]]</th><th>Type</th><td colspan="6">Bulk</td></tr>' ..
'<tr><th>Size</th><td colspan="6">[[wafer size|300 mm]]</td></tr>' ..
'<tr><th rowspan="2">xTor</th><th>Type</th><td colspan="2"></td><td colspan="2">[[FinFET]]</td><td colspan="2">[[FinFET]]</td></tr>' ..
'<tr><th>Voltage</th><td colspan="2"></td><td colspan="2"></td><td colspan="2"></td></tr>' ..
'<tr><th colspan="2">&nbsp;</th><th>Value</th><th>[[7 nm]] Δ</th><th>Value</th><th>[[7 nm]] Δ</th><th>Value</th><th>[[7 nm]] Δ</th></tr>' ..
'<tr><th rowspan="3">Fin</th><th>Pitch</th><td></td><td></td><td></td><td></td><td>27 nm</td><td>1.0x</td></tr>' ..
'<tr><th>Width</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th>Height</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th colspan="2">Gate Length (L<sub>g</sub>)</th><td></td><td></td><td></td><td></td><td>8/10 nm</td><td>1.0x</td></tr>' ..
'<tr><th colspan="2">Contacted Gate Pitch (CPP)</th><td></td><td></td><td></td><td></td><td>60 nm (HP)<br>54 nm (HD)</td><td>1.0x<br>1.0x</td></tr>' ..
'<tr><th colspan="2">Minimum Metal Pitch (MMP)</th><td></td><td></td><td></td><td></td><td>36 nm</td><td>1.0x</td></tr>' ..
'<tr><th rowspan="3">[[SRAM]]</th><th>High-Perf (HP)</th><td></td><td></td><td></td><td></td><td>0.032 µm²</td><td>1.0x</td></tr>' ..
'<tr><th>High-Density (HD)</th><td></td><td></td><td>0.021 µm²</td><td>0.78x</td><td>0.026 µm²</td><td>1.0x</td></tr>' ..
'<tr><th>Low-Voltage (LV)</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'</table>'
	end

    if arg('node') == '7 nm' then
    	return '' ..
'<table class="wikitable" style="text-align: center;">' .. 
'<tr><th colspan="2">&nbsp;</th><th colspan="2">[[Intel]]</th><th colspan="2">[[TSMC]]</th><th colspan="2">[[Samsung]]</th><th colspan="2">[[GlobalFoundries]]</th></tr>' .. 
'<tr><th colspan="2">Process</th><td colspan="2">P1276 (CPU), P1277 (SoC)</td><td colspan="2">N7, N7P, N7+</td><td colspan="2">7LPE, 7LPP</td><td colspan="2"><s>7LP, 7HP</s></td></tr>' .. 
'<tr><th colspan="2">Production</th><td colspan="2">2021</td><td colspan="2">April 2018</td><td colspan="2">April 2019</td><td colspan="2">Cancelled</td></tr>' .. 
'<tr><th rowspan="2">Litho</th><th>Lithography</th><td colspan="2">[[EUV]]</td><td colspan="2">DUV \'\'\'⇒\'\'\' EUV</td><td colspan="2">EUV</td><td colspan="2">DUV \'\'\'⇒\'\'\' EUV</td></tr>' .. 
'<tr><th>Immersion<br>Exposure</th><td colspan="2"></td><td colspan="2">SADP \'\'\'⇒\'\'\' SE (EUV)<br>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; DP (193i)</td><td colspan="2">SE (EUV)<br>DP (193i)</td><td colspan="2">SADP \'\'\'⇒\'\'\' SE (EUV)<br>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; DP (193i)</td></tr>' .. 
'<tr><th rowspan="2">[[Wafer]]</th><th>Type</th><td colspan="8">Bulk</td></tr>' .. 
'<tr><th>Size</th><td colspan="8">[[wafer size|300 mm]]</td></tr>' .. 
'<tr><th rowspan="2">xTor</th><th>Type</th><td colspan="2"></td><td colspan="6">[[FinFET]]</td></tr>' .. 
'<tr><th>Voltage</th><td colspan="2"></td><td colspan="2"></td><td colspan="2"></td><td colspan="2"></td></tr>' .. 
'<tr><th colspan="2">&nbsp;</th><th>Value</th><th>[[10 nm]] Δ</th><th>Value</th><th>[[10 nm]] Δ</th><th>Value</th><th>[[10 nm]] Δ</th><th>Value</th><th>[[14 nm]] Δ</th></tr>' .. 
'<tr><th rowspan="3">Fin</th><th>Pitch</th><td></td><td></td><td>30 nm</td><td>0.83x</td><td>27 nm</td><td>0.64x</td><td>30 nm</td><td>0.625x</td></tr>' .. 
'<tr><th>Width</th><td></td><td></td><td>6 nm</td><td>1.00x</td><td></td><td></td><td></td><td></td></tr>' .. 
'<tr><th>Height</th><td></td><td></td><td>52 nm</td><td>1.24x</td><td></td><td></td><td></td><td></td></tr>' .. 
'<tr><th colspan="2">Gate Length (L<sub>g</sub>)</th><td></td><td></td><td></td><td></td><td>8/10 nm</td><td></td><td></td><td></td></tr>' .. 
'<tr><th colspan="2">Contacted Gate Pitch (CPP)</th><td></td><td></td><td>64 nm (HP)<br>57 nm (HD)</td><td><br>0.82x</td><td>60 nm (HP)<br>54 nm (HD)</td><td><br>0.79x</td><td>56 nm</td><td>0.72x</td></tr>' .. 
'<tr><th colspan="2">Minimum Metal Pitch (MMP)</th><td></td><td></td><td>40 nm</td><td>0.95x</td><td>36 nm</td><td>0.75x</td><td>40 nm</td><td>0.625x</td></tr>' .. 
'<tr><th rowspan="3">[[SRAM]]</th><th>High-Perf (HP)</th><td></td><td></td><td></td><td></td><td>0.032 µm²</td><td>0.65x</td><td>0.0353 µm²</td><td>0.44x</td></tr>' .. 
'<tr><th>High-Density (HD)</th><td></td><td></td><td>0.027 µm²</td><td>0.64x</td><td>0.026 µm²</td><td>0.65x</td><td>0.0269 µm²</td><td>0.42x</td></tr>' .. 
'<tr><th>Low-Voltage (LV)</th><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>' .. 
'</table>'
	end

end


return node