From WikiChip
Editing 7 nm lithography process
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 5: | Line 5: | ||
== Overview == | == Overview == | ||
− | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low | + | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel [[10 nm process]] is comparable to the foundry 7-nanometer node. |
=== Density === | === Density === | ||
Line 13: | Line 13: | ||
== Industry == | == Industry == | ||
− | + | Only three companies are currently planning or developing a 7-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]]. | |
{{node comp|node=7 nm}} | {{node comp|node=7 nm}} | ||
=== Intel === | === Intel === | ||
− | ==== | + | ==== P1276 ==== |
− | + | Intel's 7-nanometer process, '''P1276''', will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. | |
− | + | ||
− | + | Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 million [[transistors per square millimeter]]. | |
=== TSMC === | === TSMC === | ||
Line 170: | Line 170: | ||
** {{apple|A13}} | ** {{apple|A13}} | ||
* HiSilicon (Huawei) | * HiSilicon (Huawei) | ||
− | ** {{hisilicon|kirin|990 | + | ** {{hisilicon|kirin|990}} |
** {{hisilicon|kirin|980}} | ** {{hisilicon|kirin|980}} | ||
** {{hisilicon|kirin|810}} | ** {{hisilicon|kirin|810}} | ||
Line 177: | Line 177: | ||
** {{qualcomm|snapdragon 855|855}} | ** {{qualcomm|snapdragon 855|855}} | ||
** {{qualcomm|snapdragon 865|865}} | ** {{qualcomm|snapdragon 865|865}} | ||
− | |||
− | |||
* Exynos (Samsung) | * Exynos (Samsung) | ||
** {{samsung|exynos 990|990}} | ** {{samsung|exynos 990|990}} |