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Editing 7 nm lithography process
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== Overview == | == Overview == | ||
− | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low | + | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel [[10 nm process]] is comparable to the foundry 7-nanometer node. |
=== Density === | === Density === | ||
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== Industry == | == Industry == | ||
− | + | Only three companies are currently planning or developing a 7-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]]. | |
{{node comp|node=7 nm}} | {{node comp|node=7 nm}} | ||
=== Intel === | === Intel === | ||
− | ==== | + | ==== P1276 ==== |
− | + | Intel's 7-nanometer process, '''P1276''', will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. | |
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− | + | Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 [[transistors per square millimeter]]. | |
=== TSMC === | === TSMC === | ||
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==== N7+ ==== | ==== N7+ ==== | ||
− | The '''N7+ node''' is TSMC's first process technology to adopt [[EUV lithography]]. It is unrelated to | + | The '''N7+ node''' is TSMC's first process technology to adopt [[EUV lithography]]. It is unrelated to N7 nor N7P and is not IP-compatible with either, requiring re-implementation (new physical layout and validation). N7+ entered mass production in the second quarter of 2019 and uses EUV for four critical layers. Compared to TSMC N7 process, N7+ is said to deliver around 1.2x density improvement. N7+ is also said to deliver 10% higher performance at iso-power or, alternatively, up to 15% lower power at iso-performance. On paper, N7+ appears to be marginally better than N7P, albeit that comes at the cost of re-implementing the design. |
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* MediaTek | * MediaTek | ||
** {{mediatek|helio|Helio M70}} | ** {{mediatek|helio|Helio M70}} | ||
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* Apple | * Apple | ||
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* HiSilicon (Huawei) | * HiSilicon (Huawei) | ||
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** {{hisilicon|kirin|980}} | ** {{hisilicon|kirin|980}} | ||
** {{hisilicon|kirin|810}} | ** {{hisilicon|kirin|810}} | ||
* Snapdragon (Qualcomm) | * Snapdragon (Qualcomm) | ||
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** {{qualcomm|snapdragon 855|855}} | ** {{qualcomm|snapdragon 855|855}} | ||
** {{qualcomm|snapdragon 865|865}} | ** {{qualcomm|snapdragon 865|865}} | ||
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* Exynos (Samsung) | * Exynos (Samsung) | ||
** {{samsung|exynos 990|990}} | ** {{samsung|exynos 990|990}} |