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{{lithography processes}} | {{lithography processes}} | ||
− | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process | + | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process begun in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]]. |
The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | ||
== Overview == | == Overview == | ||
− | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low | + | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel [[10 nm process]] is comparable to the foundry 7-nanometer node. |
=== Density === | === Density === | ||
− | In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90- | + | In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-105 million [[transistors per square millimeter]] based on WikiChip's own analysis. |
− | :[[File:7nm densities.svg| | + | :[[File:7nm densities.svg|600px]] |
== Industry == | == Industry == | ||
− | + | Only three companies are currently planning or developing a 5-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]]. | |
{{node comp|node=7 nm}} | {{node comp|node=7 nm}} | ||
=== Intel === | === Intel === | ||
− | ==== | + | ==== P1276 ==== |
− | + | Intel's 7-nanometer process, '''P1276''', will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. | |
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− | + | Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 [[transistors per square millimeter]]. | |
=== TSMC === | === TSMC === | ||
− | TSMC started mass production of its '''7-nanometer N7 node''' in April 2018. TSMC considers its 7-nanometer node a full node shrink over its 16-nanometer. Although TSMC has released a 10-nanometer node the year prior, the company considered its 10 nm to be a short-lived node and was intended to serve as a learning node on its way to 7. In early 2019 TSMC introduced the second version of its N7 process called '''N7P''' which provides additional performance enhancements | + | TSMC started mass production of its '''7-nanometer N7 node''' in April 2018. TSMC considers its 7-nanometer node a full node shrink over its 16-nanometer. Although TSMC has released a 10-nanometer node the year prior, the company considered its 10 nm to be a short-lived node and was intended to serve as a learning node on its way to 7. In early 2019 TSMC introduced the second version of its N7 process called '''N7P''' which provides additional performance enhancements. |
==== N7 ==== | ==== N7 ==== | ||
− | + | TSMC original '''7-nanometer N7 process''' was introduced in April 2018. Compared to its own [[16-nanometer technology]], TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power. N7 largely builds on all prior FinFET processes the company has had prevously. To that end, this is a fourth-generation FinFET, fifth-generation HKMG, gate-last, dual gate oxide process. | |
− | TSMC original '''7-nanometer N7 process''' was introduced in April 2018. Compared to its own [[16-nanometer technology]], TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power | ||
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[[File:tsmc-weff-16-10-7.svg|thumb|right|W<sub>eff</sub> for TSMC [[N16|16]], [[N10|10]], and 7 nm.]] | [[File:tsmc-weff-16-10-7.svg|thumb|right|W<sub>eff</sub> for TSMC [[N16|16]], [[N10|10]], and 7 nm.]] | ||
For N7, TSMC continued to use [[deep ultraviolet]] (DUV) 193 nm ArF Immersion lithography. The limitations of i193 dictated some of the design rules for the process. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point. Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point. The design rules for N7 are shown below. | For N7, TSMC continued to use [[deep ultraviolet]] (DUV) 193 nm ArF Immersion lithography. The limitations of i193 dictated some of the design rules for the process. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point. Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point. The design rules for N7 are shown below. | ||
− | {| class="wikitable" style="text-align: center;" | + | {| class="collapsible collapsed wikitable" style="text-align: center;" |
! colspan="4" | TSMC N7 Design Rules | ! colspan="4" | TSMC N7 Design Rules | ||
|- | |- | ||
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| M11, M12 || 720 || Single || 18x | | M11, M12 || 720 || Single || 18x | ||
|} | |} | ||
− | + | [[File:mss-n7-a12.jpg|right|thumb|Elements distribution of Apple's A12 SoC by MSS Corp. Cobalt contacts can be seen.]] | |
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− | [[File:mss-n7-a12.jpg|right|thumb|Elements distribution of Apple's A12 SoC | ||
The transistor profile has been enhanced as well. Like [[Intel's 10 nm process]], TSMC introduced cobalt fill at the [[trench contacts]], replacing the tungsten contact. This has the effect of reducing the resistance in that area by 50%. Some of the area scaling and cost benefits were achieved through [[fin pitch]]/[[fin height|height]] [[scaling]]. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and [[subthreshold slope]] (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I [[device delay]] is still better because the [[intrinsic capacitance]] like the [[Cgate]] and [[Cov]] still scale with [[Ieff]]. | The transistor profile has been enhanced as well. Like [[Intel's 10 nm process]], TSMC introduced cobalt fill at the [[trench contacts]], replacing the tungsten contact. This has the effect of reducing the resistance in that area by 50%. Some of the area scaling and cost benefits were achieved through [[fin pitch]]/[[fin height|height]] [[scaling]]. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and [[subthreshold slope]] (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I [[device delay]] is still better because the [[intrinsic capacitance]] like the [[Cgate]] and [[Cov]] still scale with [[Ieff]]. | ||
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Different multi-Vt devices were developed for this process with a Vt range of around 200 mV. | Different multi-Vt devices were developed for this process with a Vt range of around 200 mV. | ||
− | + | TSMC 7-nanometer comes in two variations - low power and high performance. Those [[standard cell|cells]] are 240 nm and 300 nm tall respectively. | |
− | TSMC 7-nanometer | ||
<table class="wikitable" style="text-align: center;"> | <table class="wikitable" style="text-align: center;"> | ||
− | <tr><th>Type</th><th> | + | <tr><th>Type</th><th>Low Power</th><th>High Performance</th></tr> |
− | + | <tr><th>Fin Pitch</th><td colspan="2">30 nm</td></tr> | |
− | <tr><th>Fin Pitch</th><td colspan=" | + | <tr><th>Metal</th><td colspan="2">40 nm (smallest pitch used with DP)<br>76 nm (smallest pitch used with SP)</td></tr> |
− | <tr><th>Metal</th><td colspan=" | + | <tr><th>Gate Pitch</th><td>57 nm</td><td>64 nm</td></tr> |
− | <tr><th>Gate Pitch</th><td>57 nm</td><td>64 | + | <tr><th>Height</th><td>240 nm<br>8-fin x 30 nm</td><td>300 nm<br>10-fin x 30 nm</td></tr> |
− | <tr><th>Height</th><td>240 nm<br>8-fin x 30 nm</td><td>300 nm<br>10 | + | <tr><th>Tracks</th><td>6 T</td><td>7.5 T</td></tr> |
− | <tr><th>Tracks</th><td>6 T</td><td>7.5 | ||
</table> | </table> | ||
[[File:n7_cell_height.svg|500px]] | [[File:n7_cell_height.svg|500px]] | ||
− | [[File:sdm855-n7-hd-hp-ieff.png|thumb|right|Qualcomm's [[Snapdragon 855]] [[Ieff]] difference between the HD and HP cells. | + | [[File:sdm855-n7-hd-hp-ieff.png|thumb|right|Qualcomm's [[Snapdragon 855]] self-reported [[Ieff]] difference between the HD and HP cells.]] |
Qualcomm reported that on its own SoC ([[Snapdragon 855]]), the high-performance cells deliver around 10-13% higher effective drive current ([[Ieff]]), albeit at the cost of being slightly leakier transistors. Based on WikiChip's own analysis, the dense cells come at around 91.2 [[MTr/mm²]] while the less dense, high-performance cells, are calculated at around 65 MTr/mm². | Qualcomm reported that on its own SoC ([[Snapdragon 855]]), the high-performance cells deliver around 10-13% higher effective drive current ([[Ieff]]), albeit at the cost of being slightly leakier transistors. Based on WikiChip's own analysis, the dense cells come at around 91.2 [[MTr/mm²]] while the less dense, high-performance cells, are calculated at around 65 MTr/mm². | ||
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− | ==== | + | ==== N7P ==== |
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=== Samsung === | === Samsung === | ||
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* MediaTek | * MediaTek | ||
** {{mediatek|helio|Helio M70}} | ** {{mediatek|helio|Helio M70}} | ||
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* Apple | * Apple | ||
** {{apple|A12}} | ** {{apple|A12}} | ||
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** {{apple|A13}} | ** {{apple|A13}} | ||
* HiSilicon (Huawei) | * HiSilicon (Huawei) | ||
− | ** {{hisilicon|kirin|990 | + | ** {{hisilicon|kirin|990}} |
** {{hisilicon|kirin|980}} | ** {{hisilicon|kirin|980}} | ||
** {{hisilicon|kirin|810}} | ** {{hisilicon|kirin|810}} | ||
* Snapdragon (Qualcomm) | * Snapdragon (Qualcomm) | ||
− | + | ** {{qualcomm|snapdragon 800|855}} | |
− | ** {{qualcomm|snapdragon | ||
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{{expand list}} | {{expand list}} | ||
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* {{intel|process|Intel process technology history}} | * {{intel|process|Intel process technology history}} | ||
− | == | + | == References == |
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