From WikiChip
Editing 7 nm lithography process
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
− | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. | + | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of [[integrated circuit]] using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by [[5 nm lithography process|5 nm process]] around 2022. |
− | + | == Industry == | |
+ | Only four semiconductor foundries are able to develop the advanced 7nm: [[Intel]], [[Samsung]], [[TSMC]], and [[GlobalFoundries]]. | ||
− | + | {{future information}} | |
− | |||
− | |||
− | |||
− | + | {{finfet nodes comp | |
+ | <!-- Intel --> | ||
+ | | process 1 fab = [[Intel]] | ||
+ | | process 1 name = P1276 (CPU), P1277 (SoC) | ||
+ | | process 1 date = | ||
+ | | process 1 lith = | ||
+ | | process 1 immersion = | ||
+ | | process 1 exposure = | ||
+ | | process 1 wafer type = Bulk | ||
+ | | process 1 wafer size = 300 nm | ||
+ | | process 1 transistor = | ||
+ | | process 1 volt = | ||
+ | | process 1 delta from = [[10 nm]] Δ | ||
+ | | process 1 fin pitch = | ||
+ | | process 1 fin pitch Δ = | ||
+ | | process 1 fin width = | ||
+ | | process 1 fin width Δ = | ||
+ | | process 1 fin height = | ||
+ | | process 1 fin height Δ = | ||
+ | | process 1 gate len = | ||
+ | | process 1 gate len Δ = | ||
+ | | process 1 cpp = | ||
+ | | process 1 cpp Δ = | ||
+ | | process 1 mmp = | ||
+ | | process 1 mmp Δ = | ||
+ | | process 1 sram hp = | ||
+ | | process 1 sram hp Δ = | ||
+ | | process 1 sram hd = | ||
+ | | process 1 sram hd Δ = | ||
+ | | process 1 sram lv = | ||
+ | | process 1 sram lv Δ = | ||
+ | | process 1 dram = | ||
+ | | process 1 dram Δ = | ||
+ | <!-- TSMC --> | ||
+ | | process 2 fab = [[TSMC]] | ||
+ | | process 2 name = | ||
+ | | process 2 date = | ||
+ | | process 2 lith = 193 nm | ||
+ | | process 2 immersion = Yes | ||
+ | | process 2 exposure = LELELELE | ||
+ | | process 2 wafer type = Bulk | ||
+ | | process 2 wafer size = 300 nm | ||
+ | | process 2 transistor = FinFET | ||
+ | | process 2 volt = | ||
+ | | process 2 delta from = [[10 nm]] Δ | ||
+ | | process 2 fin pitch = | ||
+ | | process 2 fin pitch Δ = | ||
+ | | process 2 fin width = | ||
+ | | process 2 fin width Δ = | ||
+ | | process 2 fin height = | ||
+ | | process 2 fin height Δ = | ||
+ | | process 2 gate len = | ||
+ | | process 2 gate len Δ = | ||
+ | | process 2 cpp = 54 | ||
+ | | process 2 cpp Δ = 0.84x | ||
+ | | process 2 mmp = 40 | ||
+ | | process 2 mmp Δ = 0.95x | ||
+ | | process 2 sram hp = | ||
+ | | process 2 sram hp Δ = | ||
+ | | process 2 sram hd = 0.027 µm² | ||
+ | | process 2 sram hd Δ = 0.64x | ||
+ | | process 2 sram lv = | ||
+ | | process 2 sram lv Δ = | ||
+ | | process 2 dram = | ||
+ | | process 2 dram Δ = | ||
+ | <!-- GlobalFoundries --> | ||
+ | | process 3 fab = [[GlobalFoundries]] | ||
+ | | process 3 name = | ||
+ | | process 3 date = 2019 | ||
+ | | process 3 lith = 193 nm | ||
+ | | process 3 immersion = Yes | ||
+ | | process 3 exposure = SAQP | ||
+ | | process 3 wafer type = Bulk | ||
+ | | process 3 wafer size = 300 nm | ||
+ | | process 3 transistor = FinFET | ||
+ | | process 3 volt = 0.75 V | ||
+ | | process 3 delta from = [[10 nm]] Δ | ||
+ | | process 3 fin pitch = | ||
+ | | process 3 fin pitch Δ = | ||
+ | | process 3 fin width = | ||
+ | | process 3 fin width Δ = | ||
+ | | process 3 fin height = | ||
+ | | process 3 fin height Δ = | ||
+ | | process 3 gate len = | ||
+ | | process 3 gate len Δ = | ||
+ | | process 3 cpp = | ||
+ | | process 3 cpp Δ = | ||
+ | | process 3 mmp = | ||
+ | | process 3 mmp Δ = | ||
+ | | process 3 sram hp = | ||
+ | | process 3 sram hp Δ = | ||
+ | | process 3 sram hd = | ||
+ | | process 3 sram hd Δ = | ||
+ | | process 3 sram lv = | ||
+ | | process 3 sram lv Δ = | ||
+ | | process 3 dram = | ||
+ | | process 3 dram Δ = | ||
+ | <!-- Samsung --> | ||
+ | | process 4 fab = [[Samsung]] | ||
+ | | process 4 name = | ||
+ | | process 4 date = 2019 | ||
+ | | process 4 lith = EUV | ||
+ | | process 4 immersion = | ||
+ | | process 4 exposure = SE | ||
+ | | process 4 wafer type = Bulk | ||
+ | | process 4 wafer size = 300 nm | ||
+ | | process 4 transistor = FinFET | ||
+ | | process 4 volt = | ||
+ | | process 4 delta from = [[10 nm]] Δ | ||
+ | | process 4 fin pitch = | ||
+ | | process 4 fin pitch Δ = | ||
+ | | process 4 fin width = | ||
+ | | process 4 fin width Δ = | ||
+ | | process 4 fin height = | ||
+ | | process 4 fin height Δ = | ||
+ | | process 4 gate len = | ||
+ | | process 4 gate len Δ = | ||
+ | | process 4 cpp = | ||
+ | | process 4 cpp Δ = | ||
+ | | process 4 mmp = | ||
+ | | process 4 mmp Δ = | ||
+ | | process 4 sram hp = | ||
+ | | process 4 sram hp Δ = | ||
+ | | process 4 sram hd = | ||
+ | | process 4 sram hd Δ = | ||
+ | | process 4 sram lv = | ||
+ | | process 4 sram lv Δ = | ||
+ | | process 4 dram = | ||
+ | | process 4 dram Δ = | ||
+ | <!-- Common Platform --> | ||
+ | | process 5 fab = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper | ||
+ | | process 5 name = | ||
+ | | process 5 date = | ||
+ | | process 5 lith = EUV | ||
+ | | process 5 immersion = | ||
+ | | process 5 exposure = SE | ||
+ | | process 5 wafer type = Bulk | ||
+ | | process 5 wafer size = 300 nm | ||
+ | | process 5 transistor = FinFet | ||
+ | | process 5 volt = | ||
+ | | process 5 delta from = [[10 nm]] Δ | ||
+ | | process 5 fin pitch = | ||
+ | | process 5 fin pitch Δ = | ||
+ | | process 5 fin width = | ||
+ | | process 5 fin width Δ = | ||
+ | | process 5 fin height = | ||
+ | | process 5 fin height Δ = | ||
+ | | process 5 gate len = | ||
+ | | process 5 gate len Δ = | ||
+ | | process 5 cpp = 48 nm | ||
+ | | process 5 cpp Δ = 0.75x | ||
+ | | process 5 mmp = 36 nm | ||
+ | | process 5 mmp Δ = 0.75x | ||
+ | | process 5 sram hp = | ||
+ | | process 5 sram hp Δ = | ||
+ | | process 5 sram hd = | ||
+ | | process 5 sram hd Δ = | ||
+ | | process 5 sram lv = | ||
+ | | process 5 sram lv Δ = | ||
+ | | process 5 dram = | ||
+ | | process 5 dram Δ = | ||
+ | }} | ||
− | == | + | === Intel === |
− | + | On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the [[5 nm]] and [[3 nm]] nodes. Intel has been maintaining the details of their 7 nm node secrete for now. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June. | |
− | + | === GlobalFoundries === | |
− | + | On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready. | |
− | === | ||
− | |||
− | |||
− | |||
− | |||
=== TSMC === | === TSMC === | ||
− | + | In ISSCC 2017, the memory group at [[TSMC]] detailed their test 256 MiB SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using 4P4E LELELELE patterning technique. The over die is 0.34x smaller than their [[16 nm process]] version. | |
− | |||
− | |||
− | |||
− | TSMC | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | {| class="wikitable" | + | {| class="collapsible collapsed wikitable" |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | ! colspan="2" | TSMC 256 Mib SRAM demo 7 nm wafer |
|- | |- | ||
− | | | + | | |
− | + | <table class="wikitable"> | |
− | + | <tr><th>Technology</th><td>7 nm HK-MG FinFET</td></tr> | |
− | + | <tr><th>Metal scheme</th><td>1 Poly / 7 Metal</td></tr> | |
− | + | <tr><th>Supply voltage</th><td>0.75 V (core)<br>1.8 V (i/o)</td></tr> | |
− | + | <tr><th>Bit cell size</th><td>0.027 µm²</td></tr> | |
− | + | <tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr> | |
− | + | <tr><th>Capacity</th><td>256 Mib</td></tr> | |
− | + | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr> | |
− | + | <tr><th>Die Size</th><td>5903 µm x 7223 µm = 42.64 mm²</td></tr> | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | <table class="wikitable | ||
− | <tr><th> | ||
− | <tr><th> | ||
− | <tr><th> | ||
− | <tr><th> | ||
− | <tr><th> | ||
− | <tr><th> | ||
− | <tr><th> | ||
</table> | </table> | ||
− | + | | [[File:tsmc 7nm SRAM block.png]] | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | [[File: | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== 7 nm Microprocessors== | == 7 nm Microprocessors== | ||
Line 160: | Line 202: | ||
** {{pezy|PEZY-SC3}} | ** {{pezy|PEZY-SC3}} | ||
* MediaTek | * MediaTek | ||
− | ** {{mediatek | + | ** {{mediatek|Helio}} |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
{{expand list}} | {{expand list}} | ||
== 7 nm Microarchitectures== | == 7 nm Microarchitectures== | ||
* AMD | * AMD | ||
− | |||
− | |||
** {{amd|Zen 2|l=arch}} | ** {{amd|Zen 2|l=arch}} | ||
** {{amd|Zen 3|l=arch}} | ** {{amd|Zen 3|l=arch}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | == | + | == References == |
− | * | + | * Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. |
− | * | + | * Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016. |
− | * | + | * Samsung/GlobalFoundries, [[IEEE]] [[International Electron Devices Meeting]] (IEDM) 2016 |
− | + | [[Category:Lithography]] |