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{{lithography processes}} | {{lithography processes}} | ||
− | The ''' | + | The '''40 nm lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[45 nm lithography process|45 nm]] and [[32 nm lithography process|32 nm]] processes. Commercial [[integrated circuit]] manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as [[TSMC]]. This technology superseded by commercial [[32 nm lithography process|32 nm process]] by 2010. |
== Industry == | == Industry == | ||
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{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Wafer | |Wafer | ||
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|Contacted Gate Pitch | |Contacted Gate Pitch | ||
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| colspan="8" | 300mm | | colspan="8" | 300mm | ||
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! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ | ! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ | ||
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== 40 nm Microprocessors == | == 40 nm Microprocessors == | ||
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{{expand list}} | {{expand list}} | ||
− | + | == 40 nm System on Chips == | |
− | + | {{expand list}} |