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Editing 280 nm lithography process
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== Industry == | == Industry == | ||
− | Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process | + | Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process. The process was used in Intel's {{intel|P55C}} and |
+ | {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors). | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
|1st Production | |1st Production | ||
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|Contacted Gate Pitch | |Contacted Gate Pitch | ||
|Interconnect Pitch (M1P) | |Interconnect Pitch (M1P) | ||
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| 1996 || 1997 | | 1996 || 1997 | ||
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| ? nm || ? nm | | ? nm || ? nm | ||
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− | | | + | | ? nm || ? nm |
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| 4 || ? | | 4 || ? | ||
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* Intel {{intel|P6|l=arch}} | * Intel {{intel|P6|l=arch}} | ||
{{expand list}} | {{expand list}} | ||
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