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{{lithography processes}} | {{lithography processes}} | ||
− | The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm process]]. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and | + | The '''14 nanometer (14 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[22 nm process]]. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and is currently getting replaced by the [[10 nm process]]. |
== Industry == | == Industry == | ||
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| process 1 lith = 193 nm | | process 1 lith = 193 nm | ||
| process 1 immersion = Yes | | process 1 immersion = Yes | ||
− | | process 1 exposure = | + | | process 1 exposure = |
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
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| process 1 dram Δ = | | process 1 dram Δ = | ||
<!-- Samsung --> | <!-- Samsung --> | ||
− | | process 2 fab = [[Samsung]]<info>'''Samsung''' consists of a process development collaboration between [[Samsung]] and [[GlobalFoundries]]. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.</info> | + | | process 2 fab = [[Samsung]] Alliance<info>'''Samsung Alliance''' consists of a process development collaboration between [[Samsung]] and [[GlobalFoundries]]. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.</info> |
| process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | | process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | ||
| process 2 date = 2015 | | process 2 date = 2015 | ||
| process 2 lith = 193 nm | | process 2 lith = 193 nm | ||
− | | process 2 immersion = | + | | process 2 immersion = |
− | | process 2 exposure = | + | | process 2 exposure = |
| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
| process 2 wafer size = 300 mm | | process 2 wafer size = 300 mm | ||
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| process 2 fin width = 8 nm | | process 2 fin width = 8 nm | ||
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
− | | process 2 fin height = | + | | process 2 fin height = ~38 nm |
| process 2 fin height Δ = | | process 2 fin height Δ = | ||
| process 2 gate len = 30 nm | | process 2 gate len = 30 nm | ||
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| process 2 dram Δ = | | process 2 dram Δ = | ||
<!-- IBM --> | <!-- IBM --> | ||
− | | process 3 fab = [[IBM]] | + | | process 3 fab = [[IBM]] |
| process 3 name = 14HP<info>14nm High Performance</info> | | process 3 name = 14HP<info>14nm High Performance</info> | ||
− | | process 3 date = | + | | process 3 date = |
| process 3 lith = 193 nm | | process 3 lith = 193 nm | ||
− | | process 3 immersion = | + | | process 3 immersion = |
− | | process 3 exposure = | + | | process 3 exposure = |
| process 3 wafer type = SOI | | process 3 wafer type = SOI | ||
| process 3 wafer size = 300 mm | | process 3 wafer size = 300 mm | ||
| process 3 transistor = FinFET | | process 3 transistor = FinFET | ||
− | | process 3 volt = 0. | + | | process 3 volt = 0.8 V |
| process 3 delta from = [[22 nm]] Δ | | process 3 delta from = [[22 nm]] Δ | ||
| process 3 fin pitch = 42 nm | | process 3 fin pitch = 42 nm | ||
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| process 3 fin height = 25 nm | | process 3 fin height = 25 nm | ||
| process 3 fin height Δ = | | process 3 fin height Δ = | ||
− | | process 3 gate len = | + | | process 3 gate len = ~20< nm |
− | | process 3 gate len Δ = | + | | process 3 gate len Δ = |
| process 3 cpp = 80 nm | | process 3 cpp = 80 nm | ||
| process 3 cpp Δ = 0.80x | | process 3 cpp Δ = 0.80x | ||
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| process 4 fab = [[UMC]] | | process 4 fab = [[UMC]] | ||
| process 4 name = | | process 4 name = | ||
− | | process 4 date = | + | | process 4 date = |
| process 4 lith = 193 nm | | process 4 lith = 193 nm | ||
− | | process 4 immersion = | + | | process 4 immersion = |
| process 4 exposure = | | process 4 exposure = | ||
− | | process 4 wafer type = | + | | process 4 wafer type = |
| process 4 wafer size = 300 mm | | process 4 wafer size = 300 mm | ||
| process 4 transistor = FinFET | | process 4 transistor = FinFET | ||
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| process 5 dram = | | process 5 dram = | ||
| process 5 dram Δ = | | process 5 dram Δ = | ||
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}} | }} | ||
=== Composition === | === Composition === | ||
[[File:intel 14nm relative density.png|left|200px]][[File:relative percentage of elements on 14nm chip.png|right|400px]] | [[File:intel 14nm relative density.png|left|200px]][[File:relative percentage of elements on 14nm chip.png|right|400px]] | ||
− | It's important | + | It's important tot note that not all processes compete with each other. The process should cater to the products that will make use of the underlying technology. The composition of the actual integrated circuit also varies by manufacturer and by design due to different goals. For example, the cache on [[Apple]]'s 14 nm {{apple|A9}} (manufactured by Samsung) accounts almost 1/3 of the entire chip whereas [[Intel]]'s {{intel|Broadwell|l=arch}} cache accounts for only 10% of the entire chip. Likewise, [[Intel]]'s {{intel|Broadwell|l=arch}} and {{intel|Skylake|l=arch}} target high-performance and incorporate a large amount of higher-speed elements which are inherently sparse. Tall cells account for almost 30% Skylake's composition and less than 1% on Apple's {{apple|A8}} or {{apple|A9}}. |
− | It should be noted that [[SRAM]] is the | + | It should be noted that [[SRAM]] is the least dense component of the process in a chip, with sometimes up to three or four times less than the density of logic cells that are used in the same process. In recent years, SRAM hasn't scaled as well as logic and I/O have either. |
=== Intel === | === Intel === | ||
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=== IBM === | === IBM === | ||
− | + | IBM developed their own "14HP" (14nm High-Performance) process at their East Fishkill, NY plant. Note that the plant AND the process, along with numerous semiconductor technology IPs, were sold to [[GlobalFoundries]] in late 2014. GF still operates the plant (also by ex-IBM semicondcutor engineers) and the process which is used by IBM for their various processors. This process was designed by IBM for their very large chips with effective power supply and clock distribution capable of producing dies as large as 700 mm² and larger with a hierarchical [[BEOL]] of 17 levels of copper interconnect for high performance wire-ability. It should be noted that GlobalFoundries had no such capabilities prior to their acquisition of IBM's plant, semiconductor manufacturing group, and IP portfolio. | |
− | |||
− | IBM developed their own "14HP" (14nm High-Performance) process at their East Fishkill, NY plant. Note that the plant AND the process, along with numerous semiconductor technology IPs, were sold to [[GlobalFoundries]] in late 2014. GF still operates the plant (also by ex-IBM | ||
− | IBM's HP 14nm CMOS process features a [[FinFET]] architecture on an [[silicon-on-insulator|SOI]] substrate. The use of SOI with [[ | + | IBM's HP 14nm CMOS process features a [[FinFET]] architecture on an [[silicon-on-insulator|SOI]] substrate. The use of SOI with [[FinFet]] gives IBM a number of unique advantages such as lower [[parasitic capacitance]] at the base of the fin as well as simplifies patterning of the active fins and minimizes their variability such as height and thickness. The architecture also includes high-density deep-trench [[embedded DRAM]] cells with a reported size of 0.0174 µm². The process features an L<sub>gate</sub> of 20nm and smaller (18nm to 27nm) which IBM reported to result in over 35% performance gain verses their HP 22nm process (for identical V<sub>dd</sub> = 0.8 V). |
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=== Samsung === | === Samsung === | ||
− | + | This process became Samsungs' and GlobalFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals. | |
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− | This process became | ||
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== Find models == | == Find models == | ||
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== 14 nm Microprocessors== | == 14 nm Microprocessors== | ||
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* Intel | * Intel | ||
{{collist | {{collist | ||
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* {{intel|Core i7}} | * {{intel|Core i7}} | ||
* {{intel|Core i7EE}} | * {{intel|Core i7EE}} | ||
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* {{intel|pentium (2009)|Pentium}} | * {{intel|pentium (2009)|Pentium}} | ||
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* {{intel|Celeron}} | * {{intel|Celeron}} | ||
* {{intel|Xeon}} | * {{intel|Xeon}} | ||
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* {{intel|Xeon Platinum}} | * {{intel|Xeon Platinum}} | ||
* {{intel|Xeon Silver}} | * {{intel|Xeon Silver}} | ||
+ | }} | ||
+ | * AMD | ||
+ | {{collist | ||
+ | | count = 4 | ||
+ | | style = padding-left: 30px | ||
+ | | | ||
+ | * {{amd|EPYC}} | ||
+ | * {{amd|Ryzen 3}} | ||
+ | * {{amd|Ryzen 5}} | ||
+ | * {{amd|Ryzen 7}} | ||
}} | }} | ||
* Samsung | * Samsung | ||
** {{samsung|Exynos}} | ** {{samsung|Exynos}} | ||
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{{expand list}} | {{expand list}} | ||
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** {{intel|Kaby Lake|l=arch}} | ** {{intel|Kaby Lake|l=arch}} | ||
** {{intel|Coffee Lake|l=arch}} | ** {{intel|Coffee Lake|l=arch}} | ||
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* AMD | * AMD | ||
** {{amd|Zen|l=arch}} | ** {{amd|Zen|l=arch}} | ||
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* IBM | * IBM | ||
** {{ibm|POWER9|l=arch}} | ** {{ibm|POWER9|l=arch}} | ||
** {{ibm|z14|l=arch}} | ** {{ibm|z14|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
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* [[:File:14-nm-technology-fact-sheet.pdf|Intel's 14 nm Technology: Delivering Ultrafast, Energy-Sipping Products]] | * [[:File:14-nm-technology-fact-sheet.pdf|Intel's 14 nm Technology: Delivering Ultrafast, Energy-Sipping Products]] | ||
* [[:File:2015 InvestorMeeting Bill Holt WEB2.pdf|Intel's 14nm, Advancing Moore's Law, investor meeting]] | * [[:File:2015 InvestorMeeting Bill Holt WEB2.pdf|Intel's 14nm, Advancing Moore's Law, investor meeting]] | ||
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== References == | == References == | ||
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* Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169. | * Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169. | ||
* Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014. | * Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014. | ||
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− | [[ | + | [[Category:Lithography]] |