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{{lithography processes}} | {{lithography processes}} | ||
− | The '''14 nanometer (14 nm) lithography process''' is a | + | The '''14 nanometer (14 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[16 nm lithography process|16 nm]] and [[10 nm lithography process|10 nm]] processes. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 14 nm process began in 2014. This technology is set to be replaced with [[10 nm lithography process|10 nm process]] in 2017. |
== Industry == | == Industry == | ||
+ | 14 nm became [[Intel]]'s 2nd generation finFET transistors. This process became Samsungs' and GlobalFoundries first generation of finFet-based transistors. Intel uses TiN pMOS / TiAlN nMOS while Samsung uses TiN pMOS / TiAIC nMOS as work function metals. Intel makes use of [[Self-Aligned Double Patterning]] (SADP) with 193 nm immersion lithography at critical patterning layers. | ||
{{finfet nodes comp | {{finfet nodes comp | ||
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| process 1 name = P1272 (CPU) / P1273 (SoC) | | process 1 name = P1272 (CPU) / P1273 (SoC) | ||
| process 1 date = 2014 | | process 1 date = 2014 | ||
− | | process 1 lith = | + | | process 1 lith = |
− | | process 1 immersion = | + | | process 1 immersion = |
− | | process 1 exposure = | + | | process 1 exposure = |
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
| process 1 transistor = FinFET | | process 1 transistor = FinFET | ||
− | | process 1 volt = | + | | process 1 volt = |
| process 1 delta from = [[22 nm]] Δ | | process 1 delta from = [[22 nm]] Δ | ||
| process 1 fin pitch = 42 nm | | process 1 fin pitch = 42 nm | ||
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| process 1 mmp Δ = 0.65x | | process 1 mmp Δ = 0.65x | ||
| process 1 sram hp = 0.0706 µm² | | process 1 sram hp = 0.0706 µm² | ||
− | | process 1 sram hp Δ = | + | | process 1 sram hp Δ = |
| process 1 sram hd = 0.0499 µm² | | process 1 sram hd = 0.0499 µm² | ||
− | | process 1 sram hd Δ = | + | | process 1 sram hd Δ = |
| process 1 sram lv = 0.0588 µm² | | process 1 sram lv = 0.0588 µm² | ||
− | | process 1 sram lv Δ = | + | | process 1 sram lv Δ = |
| process 1 dram = | | process 1 dram = | ||
| process 1 dram Δ = | | process 1 dram Δ = | ||
<!-- Samsung --> | <!-- Samsung --> | ||
− | | process 2 fab = [[Samsung]] | + | | process 2 fab = [[Samsung]] |
| process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | | process 2 name = 14LPE<info>1<sup>st</sup> generation; 14 nm Low Power Early</info>, 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info>, 14LPC<info>3<sup>rd</sup> generation; 14 nm Low Power Cost [reduced]</info>, 14LPU<info>4<sup>th</sup> generation; 14 nm Low Power Ultimate</info> | ||
− | | process 2 date = | + | | process 2 date = |
− | | process 2 lith = | + | | process 2 lith = |
− | | process 2 immersion = | + | | process 2 immersion = |
− | | process 2 exposure = | + | | process 2 exposure = |
| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
| process 2 wafer size = 300 mm | | process 2 wafer size = 300 mm | ||
| process 2 transistor = FinFET | | process 2 transistor = FinFET | ||
− | | process 2 volt = | + | | process 2 volt = |
| process 2 delta from = [[20 nm]] Δ | | process 2 delta from = [[20 nm]] Δ | ||
| process 2 fin pitch = 48 nm | | process 2 fin pitch = 48 nm | ||
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| process 2 fin width = 8 nm | | process 2 fin width = 8 nm | ||
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
− | | process 2 fin height = | + | | process 2 fin height = ~38 nm |
| process 2 fin height Δ = | | process 2 fin height Δ = | ||
| process 2 gate len = 30 nm | | process 2 gate len = 30 nm | ||
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| process 2 mmp = 64 nm | | process 2 mmp = 64 nm | ||
| process 2 mmp Δ = 1.00x | | process 2 mmp Δ = 1.00x | ||
− | | process 2 sram hp = 0. | + | | process 2 sram hp = 0.0806 µm² |
− | | process 2 sram hp Δ = | + | | process 2 sram hp Δ = |
| process 2 sram hd = 0.064 µm² | | process 2 sram hd = 0.064 µm² | ||
− | | process 2 sram hd Δ = | + | | process 2 sram hd Δ = |
| process 2 sram lv = | | process 2 sram lv = | ||
| process 2 sram lv Δ = | | process 2 sram lv Δ = | ||
| process 2 dram = | | process 2 dram = | ||
| process 2 dram Δ = | | process 2 dram Δ = | ||
− | <!-- | + | <!-- GlobalFoundries --> |
− | | process 3 fab = [[ | + | | process 3 fab = [[GlobalFoundries]] |
− | | process 3 name = | + | | process 3 name = 14LPP<info>2<sup>nd</sup> generation; 14 nm Low Power Performance</info> |
− | | process 3 date = | + | | process 3 date = |
− | | process 3 lith = | + | | process 3 lith = |
− | | process 3 immersion = | + | | process 3 immersion = |
− | | process 3 exposure = | + | | process 3 exposure = |
− | | process 3 wafer type = | + | | process 3 wafer type = Bulk |
| process 3 wafer size = 300 mm | | process 3 wafer size = 300 mm | ||
| process 3 transistor = FinFET | | process 3 transistor = FinFET | ||
− | | process 3 volt = | + | | process 3 volt = |
− | | process 3 delta from = [[ | + | | process 3 delta from = [[20 nm]] Δ |
− | | process 3 fin pitch = | + | | process 3 fin pitch = 48 nm |
| process 3 fin pitch Δ = - | | process 3 fin pitch Δ = - | ||
− | | process 3 fin width = | + | | process 3 fin width = 8 nm |
| process 3 fin width Δ = | | process 3 fin width Δ = | ||
− | | process 3 fin height = | + | | process 3 fin height = ~38 nm |
| process 3 fin height Δ = | | process 3 fin height Δ = | ||
− | | process 3 gate len = | + | | process 3 gate len = 30 nm |
− | | process 3 gate len Δ = | + | | process 3 gate len Δ = |
− | | process 3 cpp = | + | | process 3 cpp = 78 nm |
− | | process 3 cpp Δ = | + | | process 3 cpp Δ = 1.22x |
| process 3 mmp = 64 nm | | process 3 mmp = 64 nm | ||
− | | process 3 mmp Δ = | + | | process 3 mmp Δ = 1.00x |
− | | process 3 sram hp = 0. | + | | process 3 sram hp = 0.0806 µm² |
− | | process 3 sram hp Δ = | + | | process 3 sram hp Δ = |
− | | process 3 sram hd = 0. | + | | process 3 sram hd = 0.064 µm² |
− | | process 3 sram hd Δ = | + | | process 3 sram hd Δ = |
| process 3 sram lv = | | process 3 sram lv = | ||
| process 3 sram lv Δ = | | process 3 sram lv Δ = | ||
− | | process 3 dram = | + | | process 3 dram = |
− | | process 3 dram Δ = | + | | process 3 dram Δ = |
− | <!-- | + | <!-- IBM --> |
− | | process 4 fab = [[ | + | | process 4 fab = [[IBM]] |
| process 4 name = | | process 4 name = | ||
− | | process 4 date = | + | | process 4 date = |
− | | process 4 lith = | + | | process 4 lith = |
− | | process 4 immersion = | + | | process 4 immersion = |
| process 4 exposure = | | process 4 exposure = | ||
− | | process 4 wafer type = | + | | process 4 wafer type = SOI |
| process 4 wafer size = 300 mm | | process 4 wafer size = 300 mm | ||
| process 4 transistor = FinFET | | process 4 transistor = FinFET | ||
| process 4 volt = | | process 4 volt = | ||
− | | process 4 delta from = [[ | + | | process 4 delta from = [[22 nm]] Δ |
− | | process 4 fin pitch = | + | | process 4 fin pitch = 42 nm |
− | | process 4 fin pitch Δ = | + | | process 4 fin pitch Δ = - |
− | | process 4 fin width = | + | | process 4 fin width = 10 nm |
| process 4 fin width Δ = | | process 4 fin width Δ = | ||
− | | process 4 fin height = | + | | process 4 fin height = 25 nm |
| process 4 fin height Δ = | | process 4 fin height Δ = | ||
| process 4 gate len = | | process 4 gate len = | ||
| process 4 gate len Δ = | | process 4 gate len Δ = | ||
− | | process 4 cpp = | + | | process 4 cpp = 80 nm |
− | | process 4 cpp Δ = | + | | process 4 cpp Δ = 0.80x |
− | | process 4 mmp = | + | | process 4 mmp = 64 nm |
− | | process 4 mmp Δ = | + | | process 4 mmp Δ = 0.80x |
− | | process 4 sram hp = | + | | process 4 sram hp = 0.900 µm² |
| process 4 sram hp Δ = | | process 4 sram hp Δ = | ||
− | | process 4 sram hd = | + | | process 4 sram hd = 0.081 µm² |
− | | process 4 sram hd Δ = | + | | process 4 sram hd Δ = 0.81x |
| process 4 sram lv = | | process 4 sram lv = | ||
| process 4 sram lv Δ = | | process 4 sram lv Δ = | ||
− | | process 4 dram = | + | | process 4 dram = 0.0174 µm² |
− | | process 4 dram Δ = | + | | process 4 dram Δ = 0.67x |
<!-- UMC --> | <!-- UMC --> | ||
− | | process 5 fab = [[ | + | | process 5 fab = [[UMC]] |
− | | process 5 name = | + | | process 5 name = |
| process 5 date = | | process 5 date = | ||
− | | process 5 lith = | + | | process 5 lith = |
− | | process 5 immersion = | + | | process 5 immersion = |
− | | process 5 exposure = | + | | process 5 exposure = |
− | | process 5 wafer type = | + | | process 5 wafer type = |
| process 5 wafer size = 300 mm | | process 5 wafer size = 300 mm | ||
− | | process 5 transistor = | + | | process 5 transistor = FinFET |
− | | process 5 volt = | + | | process 5 volt = |
| process 5 delta from = [[28 nm]] Δ | | process 5 delta from = [[28 nm]] Δ | ||
− | | process 5 fin pitch = | + | | process 5 fin pitch = |
| process 5 fin pitch Δ = | | process 5 fin pitch Δ = | ||
| process 5 fin width = | | process 5 fin width = | ||
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| process 5 fin height = | | process 5 fin height = | ||
| process 5 fin height Δ = | | process 5 fin height Δ = | ||
− | | process 5 gate len = | + | | process 5 gate len = |
− | | process 5 gate len Δ = | + | | process 5 gate len Δ = |
− | | process 5 cpp = | + | | process 5 cpp = |
− | | process 5 cpp Δ = | + | | process 5 cpp Δ = |
− | | process 5 mmp = | + | | process 5 mmp = |
− | | process 5 mmp Δ = | + | | process 5 mmp Δ = |
− | | process 5 sram hp = | + | | process 5 sram hp = |
− | | process 5 sram hp Δ = | + | | process 5 sram hp Δ = |
− | | process 5 sram hd = | + | | process 5 sram hd = |
− | | process 5 sram hd Δ = | + | | process 5 sram hd Δ = |
| process 5 sram lv = | | process 5 sram lv = | ||
| process 5 sram lv Δ = | | process 5 sram lv Δ = | ||
| process 5 dram = | | process 5 dram = | ||
| process 5 dram Δ = | | process 5 dram Δ = | ||
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=== Intel === | === Intel === | ||
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[[File:intel 14nm gate.png|250px]] | [[File:intel 14nm gate.png|250px]] | ||
{| class="wikitable collapsible collapsed" | {| class="wikitable collapsible collapsed" | ||
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| Metal 2 || 52 || 0.65 | | Metal 2 || 52 || 0.65 | ||
|} | |} | ||
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== Find models == | == Find models == | ||
− | {{#ask: [[instance of::microprocessor]] [[process::14 nm]] | + | {{#ask: |
− | |?microprocessor family | + | [[instance of::microprocessor]] |
− | |?microarchitecture | + | [[process::14 nm]] |
− | |?process | + | | ?full page name |
− | |?designer | + | | ?name |
− | |?manufacturer | + | | ?microprocessor family |
− | |?first launched | + | | ?microarchitecture |
− | |?base frequency | + | | ?process |
− | |format= | + | | ?designer |
− | + | | ?manufacturer | |
− | + | | ?first launched | |
− | + | | ?base frequency | |
− | + | | format=template|link=all|sort=name|order=asc|headers=hide|mainlabel=-|intro=<table class="wikitable"><tr><th colspan="8">[[14 nm]] Microprocessors</th></tr><tr><th colspan="3">Model</th><th colspan="5">Specs</th></tr><tr><th>Model</th><th>Family</th><th>µarch</th><th>Process</th><th>Designer</th><th>Manufacturer</th><th>Intro</th><th>Freq</th></tr>|outro=</table>|limit=0|searchlabel=Click to browse all 14 nm MPU models|sep=,|template=proc table 1|userparam=9 | |
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}} | }} | ||
== 14 nm Microprocessors== | == 14 nm Microprocessors== | ||
+ | * Intel | ||
+ | ** {{intel|Atom x5}} | ||
+ | ** {{intel|Atom x7}} | ||
+ | ** {{intel|Core i3}} | ||
+ | ** {{intel|Core i5}} | ||
+ | ** {{intel|Core i7}} | ||
+ | ** {{intel|Core i7EE}} | ||
+ | ** {{intel|pentium (2009)|Pentium}} | ||
+ | ** {{intel|Celeron}} | ||
+ | ** {{intel|Xeon}} | ||
+ | ** {{intel|Xeon D}} | ||
+ | ** {{intel|Xeon E3}} | ||
+ | ** {{intel|Xeon E5}} | ||
+ | ** {{intel|Xeon E7}} | ||
* AMD | * AMD | ||
− | + | ** {{amd|Ryzen}} | |
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− | * | ||
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− | * {{amd|Ryzen | ||
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{{expand list}} | {{expand list}} | ||
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** {{intel|Kaby Lake|l=arch}} | ** {{intel|Kaby Lake|l=arch}} | ||
** {{intel|Coffee Lake|l=arch}} | ** {{intel|Coffee Lake|l=arch}} | ||
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* AMD | * AMD | ||
** {{amd|Zen|l=arch}} | ** {{amd|Zen|l=arch}} | ||
− | ** {{amd|Zen | + | ** {{amd|Zen 2|l=arch}} |
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* IBM | * IBM | ||
** {{ibm|POWER9|l=arch}} | ** {{ibm|POWER9|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
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== Documents == | == Documents == | ||
* [[:File:14-nm-technology-fact-sheet.pdf|Intel's 14 nm Technology: Delivering Ultrafast, Energy-Sipping Products]] | * [[:File:14-nm-technology-fact-sheet.pdf|Intel's 14 nm Technology: Delivering Ultrafast, Energy-Sipping Products]] | ||
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== References == | == References == | ||
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* Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | * Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. | ||
* Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015. | * Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015. | ||
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− | [[ | + | [[Category:Lithography]] |