Editing intel/microarchitectures/ice lake (server)

{{intel title|Ice Lake (server)|arch}}
{{microarchitecture
|atype=CPU
|name=Ice Lake (server)
|designer=Intel
|manufacturer=Intel
|introduction=April, 2021
|process=10 nm
|cores=8
|cores 2=10
|cores 3=12
|cores 4=16
|cores 5=18
|cores 6=20
|cores 7=24
|cores 8=26
|cores 9=28
|cores 10=32
|cores 11=36
|cores 12=38
|cores 13=40
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=5-way
|isa=x86-64
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=48 KiB
|l1d per=core
|l1d desc=12-way set associative
|l2=1.25 MiB
|l2 per=core
|l2 desc=20-way set associative
|l3=1.5 MiB
|l3 per=core
|l3 desc=12-way set associative
|core name=Ice Lake SP
|core name 2=Ice Lake X
|predecessor=Cooper Lake
|predecessor link=intel/microarchitectures/cooper lake
|successor=Sapphire Rapids
|successor link=intel/microarchitectures/sapphire rapids
|contemporary=Ice Lake (client)
|contemporary link=intel/microarchitectures/ice_lake_(client)
}}
'''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Target
|-
| {{intel|Ice Lake X|l=core}} || ICL-X || High-end desktops & enthusiasts market
|-
| {{intel|Ice Lake W|l=core}} || ICL-W || Enterprise/Business workstations
|-
| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors
|}

== Release Dates ==
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]]
Ice Lake server processors were said to launch in the first half of 2021.

== Process Technology==
{{see also|intel/microarchitectures/ice lake (client)#Process_Technology|l1=Ice Lake (client) § Process Technology}}
Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

== Compiler support ==
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
|-
| [[GCC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
|-
| [[LLVM]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
|-
| [[Visual Studio]] || <code>/arch=AVX512</code> || <code>/tune:?</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
| rowspan="2" | ? || 0 || 0x6 || 0x? || ?
|-
| colspan="4" | Family 6 Model ?
|-
| rowspan="2" | SP || 0 || 0x6 || 6 || A
|-
| colspan="4" | Family 6 Model 106
|}

== Architecture ==

=== Key changes from {{\\|Cascade Lake}}===
* Enhanced "10nm+" (from [[14 nm]])
* {{\\|Sunny Cove|Sunny Cove core}}
** ''See {{\\|Sunny Cove}} for microarchitectural details and changes''
* I/O
** PCIe 4.0 (from PCIe 3.0)
* Memory
** Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
** Octa-channel (up from hexa-channel) 
** 3200 MT/s (up from 2933 MT/s)
** Optane DC DIMMs
*** Apache Pass '''→''' Barlow Pass
* Platform
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
* Packaging
** 4189-contact flip-chip LGA (up from 3647 contacts)
{{expand list}}

====New instructions ====
Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.

== All Ice Lake Chips ==
{{future information}}
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc6 tc7 tc14 tc15">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="24">List of Ice Lake Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">Frequency/{{intel|Turbo Boost|Turbo}}</th><th>Mem</th><th colspan="7">Major Feature Diff</th></tr>
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, %Max Turbo, Max Mem, Turbo, SMT}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=200
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::2]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::4]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::8]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ice Lake (server)]]}}
</table>
{{comp table end}}
codename	Ice Lake (server) +
core count	8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 +
designer	Intel +
first launched	April 2021 +
full page name	intel/microarchitectures/ice lake (server) +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Ice Lake (server) +
pipeline stages (max)	19 +
pipeline stages (min)	14 +