Editing technology node

{{title|Technology Node}}{{lithography processes}}
The '''technology node''' (also '''process node''', '''process technology''' or simply '''node''') refers to a specific [[semiconductor manufacturing process]] and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. Recent technology nodes such as [[22 nm]], [[16 nm]], [[14 nm]], and [[10 nm]] refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch.  Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes.

Since around 2017 node names have been entirely overtaken by marketing with some leading-edge foundries using node names ambiguously to represent slightly modified processes. Additionally, the size, density, and performance of the transistors among foundries no longer matches between foundries. For example, Intel's [[10 nm]] is comparable to foundries [[7 nm]] while Intel's [[7 nm]] is comparable to foundries [[5 nm]].

== Nomenclature ==
The driving force behind process node scaling is [[Moore's Law]]. To achieve density doubling, the [[contacted poly pitch]] (CPP) and the [[minimum metal pitch]] (MMP) need to scale by roughly 0.7x each node. In other words, a scaling of <code>0.7x CPP ⋅ 0.7x MMP ≈ ½ area</code>. The node names are effectively a self-fulfilling prophecy driven by [[Moore's Law]].

[[File:tech node naming.svg]]
== History==
{{see also|intel/process|dec/process|l1=Intel's Semiconductor Process History||l2=DEC's Semiconductor Process History}}
Roughly for the first 35 years of the semiconductor history, since the first mass production of [[MOSFET]] in the 1960s to the late 1990s, the process node more or less referred to the transistor's [[gate length]] (L<sub>g</sub>) which was also considered the "minimum feature size". For example, [[Intel]]'s [[0.5 µm process]] had <code>L<sub>g</sub> = 0.5 µm</code>. This lasted until the [[0.25 µm process]] in [[1997]] at which point Intel started introducing more aggressive gate length scaling. For example, their [[0.25 µm process]] had <code>L<sub>g</sub> = 0.20 µm</code> and likewise, their [[0.18 µm process]] had <code>L<sub>g</sub> = 0.13 µm</code> (a node ahead). At those nodes the "process node" was effectively larger than the gate length.

<div style="display:inline-block; float: left; padding: 10px;">[[File:tech node.svg|100px]]</div>
The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while [[DRAM]] development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of [[technology scaling]]. This continued to be the case well into the 2000s. The [[International Technology Roadmap for Semiconductors]] (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for [[Flash]], [[DRAM]], and [[MPU]]/[[ASIC]].

The ITRS traditionally defined the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process. It is a common metric used to describe and differentiate the technologies used in [[fabricating]] [[integrated circuit]]s. 

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=== Meaning lost ===
At the [[45 nm process]], Intel reached a gate length of 25 nm on a traditional [[planar transistor]]. At that node the gate length scaling effectively stalled; any further scaling to the gate length would produce less desirable results. Following the [[32 nm process]] node, while other aspects of the transistor shrunk, the gate length was actually increased.

With the introduction of FinFET by Intel in their [[22 nm process]], the transistor density continued to increase all while the gate length remained more or less a constant. This is due to the properties of FinFET; for example the effective channel length is a function of the new fins (<code>W<sub>eff</sub> = 2 * H<sub>fin</sub> + W<sub>fin</sub></code>). Due to how the transistor changed dramatically from how it used to be, the current naming scheme lost any meaning.

== Half node ==
Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. [[130 nm lithography process|130 nm]] after a full shrink yields [[90 nm lithography process|90 nm]]). Similarly, the associated '''half node''' was then expected to have a 0.9x linear shrink. The premise of this idea is that when a new technology node was being considered for a new full node, foundries design rules (e.g. [[standard cell]]s) were carefully designed with the expectation that a half node shrink was to follow after 18 months. When a half shrink finally took place, it was just a matter of various readjustments. Proper planning and proactive considerations during circuit design stages could allow seamless transition to the new process without encountering design rule violations, timing, or otherwise any reliability issues. Note that some steps such as [[packaging]] do need to be redesigned.

== Leading edge trend ==
As shrinking becomes more complex, requiring more capital, expertise, and resources, the number of companies capable of providing leading edge fabrication has been steadily dropping. As of 2020, only three companies are now capable of fabricating [[integrated circuits]] on the most cutting edge process: [[Intel]], [[Samsung]], and [[TSMC]].


{| class="wikitable" style="text-align: center;"
! colspan="11" | Number of Semiconductor Manufacturers with a Cutting Edge Logic Fab
|- style="vertical-align: bottom; font-size: .8em;"
|
[[SilTerra]]<br>
[[X-FAB]]<br>
[[Dongbu HiTek]]<br>
[[ADI]]<br>
[[Atmel]]<br>
[[Rohm]]<br>
[[Sanyo]]<br>
[[Mitsubishi]]<br>
[[ON]]<br>
[[Hitachi]]<br>
[[Cypress]]<br>
[[Sony]]<br>
[[Infineon]]<br>
[[Sharp]]<br>
[[Freescale]]<br>
[[Renesas]] (NEC)<br>
[[Toshiba]]<br>
[[Fujitsu]]<br>
[[TI]]<br>
[[Panasonic]]<br>
[[STMicroelectronics]]<br>
[[HLMC]]<br>
[[UMC]]<br>
[[IBM]]<br>
[[SMIC]]<br>
[[AMD]]<br>
[[Samsung]]<br>
[[TSMC]]<br>
[[Intel]]
|
ADI<br>
Atmel<br>
Rohm<br>
Sanyo<br>
Mitsubishi<br>
ON<br>
Hitachi<br>
Cypress<br>
Sony<br>
Infineon<br>
Sharp<br>
Freescale<br>
Renesas<br>
Toshiba<br>
Fujitsu<br>
TI<br>
Panasonic<br>
STM<br>
HLMC<br>
UMC<br>
IBM<br>
SMIC<br>
AMD<br>
Samsung<br>
TSMC<br>
Intel
|
Cypress<br>
Sony<br>
Infineon<br>
Sharp<br>
Freescale<br>
Renesas<br>
Toshiba<br>
Fujitsu<br>
TI<br>
Panasonic<br>
STM<br>
<br>
UMC<br>
IBM<br>
SMIC<br>
AMD<br>
Samsung<br>
TSMC<br>
Intel
|
Renesas<br>
Toshiba<br>
Fujitsu<br>
TI<br>
Panasonic<br>
STM<br>
HLMC<br>
UMC<br>
IBM<br>
SMIC<br>
[[GlobalFoundries]]<br>
Samsung<br>
TSMC<br>
Intel
|
Renesas<br>
Toshiba<br>
Fujitsu<br>
TI<br>
Panasonic<br>
STM<br>
HLMC<br>
UMC<br>
IBM<br>
SMIC<br>
GF<br>
Samsung<br>
TSMC<br>
Intel
|
Panasonic<br>
STM<br>
HLMC<br>
UMC<br>
IBM<br>
SMIC<br>
GF<br>
Samsung<br>
TSMC<br>
Intel
|
IBM<br>
<br>
GF<br>
Samsung<br>
TSMC<br>
Intel
|
UMC<br>
<br>
SMIC<br>
GF<br>
Samsung<br>
TSMC<br>
Intel
|
SMIC<br>
<br>
Samsung<br>
TSMC<br>
Intel
|
Samsung<br>
TSMC<br>
Intel
|
Samsung<br>
TSMC<br>
|-
| [[180 nm]]
| [[130 nm]]
| [[90 nm]]
| [[65 nm]]
| [[45 nm]]/[[40 nm]]
| [[32 nm]]/[[28 nm]]
| [[22 nm]]/[[20 nm]]
| [[16 nm]]/[[14 nm]]
| [[10 nm]]
| [[7 nm]]
| [[5 nm]]
|}

[[Category:device fabrication]]