Editing intel

{{title|Intel}}
{{semi company
| name              = Intel
| logo              = Intel-logo.svg
| type              = Public
| founded           = July 18, 1968
| founded location  = Mountain View, California
| founder           = Gordon Moore
| founder 2         = Robert Noyce
| founder 3         = Andrew Grove
| headquarters      = Santa Clara, California
| website           = http://www.intel.com
| wikidata id       = Q248
| module 1          = {{manufacturer id
| logo1             = [[File:ic logo (intel).svg]]
| package1          = [[File:ic example (intel).svg]]
}}
}}
'''Intel Corporation''' is an American [[semiconductor]] company. While most notably known for their development of [[microprocessors]] and [[x86]], Intel also designs and manufactures other [[integrated circuit]]s including [[flash memory]], [[network interface controller]]s, [[GPU]]s, [[chipset]]s, motherboards, and computers.

In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to.

== Subsidiaries ==
* [[Barefoot Networks]]
* [[Movidius]]
* [[Nervana]]
* [[Mobileye]]

== Find Chip ==
* By {{intel|S-Spec}}

== List of processor families ==
{{collist
| count = 4
|
* {{intel|3000}}
* {{intel|80186}}
* {{intel|80188}}
* {{intel|80286}}
* {{intel|80376}}
* {{intel|80386}}
* {{intel|80486}}
* {{intel|Atom}}
* {{intel|Atom x3}}
* {{intel|Atom x5}}
* {{intel|Atom x7}}
* {{intel|Celeron}}
* {{intel|Celeron D}}
* {{intel|Celeron M}}
* {{intel|Core 2 Duo}}
* {{intel|Core 2 Extreme}}
* {{intel|Core 2 Quad}}
* {{intel|Core 2 Quad Extreme}}
* {{intel|Core 2 Solo}}
* {{intel|Core Duo}}
* {{intel|Core i3}}
* {{intel|Core i5}}
* {{intel|Core i7}}
* {{intel|Core i7 EE}}
* {{intel|Core i9}}
* {{intel|Core M}}
* {{intel|Core Solo}}
* {{intel|EP80579}}
* {{intel|i860}}
* {{intel|i960}}
* {{intel|iAPX432}}
* {{intel|Itanium}}
* {{intel|Itanium 2}}
* {{intel|MCS-4}}
* {{intel|MCS-40}}
* {{intel|MCS-48}}
* {{intel|MCS-51}}
* {{intel|MCS-8}}
* {{intel|MCS-80}}
* {{intel|MCS-85}}
* {{intel|MCS-86}}
* {{intel|MCS-88}}
* {{intel|MCS-96}}
* {{intel|Mobile Pentium II}}
* {{intel|Pentium}}
* {{intel|Pentium (2009)}}
* {{intel|Pentium 4}}
* {{intel|Pentium 4 EE}}
* {{intel|Pentium 4-M}}
* {{intel|Pentium D}}
* {{intel|Pentium EE}}
* {{intel|Pentium Gold}}
* {{intel|Pentium II}}
* {{intel|Pentium III}}
* {{intel|Pentium III Mobile}}
* {{intel|Pentium III Xeon}}
* {{intel|Pentium II Mobile}}
* {{intel|Pentium II Xeon}}
* {{intel|Pentium M}}
* {{intel|Pentium MMX}}
* {{intel|Pentium Pro}}
* {{intel|Pentium Silver}}
* {{intel|PXA}}
* {{intel|Quark}}
* {{intel|Xeon}}
* {{intel|Xeon Bronze}}
* {{intel|Xeon D}}
* {{intel|Xeon E}}
* {{intel|Xeon E3}}
* {{intel|Xeon E5}}
* {{intel|Xeon E7}}
* {{intel|Xeon Gold}}
* {{intel|Xeon Platinum}}
* {{intel|Xeon Silver}}
* {{intel|Xeon W}}
}}

== List of architectures ==
{{collist
| count = 1
|
* {{\\|MCS-8/ISA|MCS-8 (8008)}}
* [[x86]]
* {{\\|Configurable Spatial Accelerator}} (CSA)
* {{\\|Programmable Unified Memory Architecture}} (PUMA)
}}

== List of microarchitectures ==
'''Mainstream ([[x86]]):'''
{{collist
| count = 4
|
* {{intel|80186|l=arch}}
* {{intel|80286|l=arch}}
* {{intel|80386|l=arch}}
* {{intel|80486|l=arch}}
* {{intel|P5|l=arch}}
* {{intel|P6|l=arch}}
* {{intel|NetBurst|l=arch}}
* {{intel|Enhanced NetBurst|l=arch}}
}}


{{collist
| count = 4
| style= margin-left: 20px;
|
'''Client SoC:'''
* {{intel|Core (client)|l=arch}}
* {{intel|Penryn (client)|l=arch}}
* {{intel|Nehalem (client)|l=arch}}
* {{intel|Westmere (client)|l=arch}}
* {{intel|Sandy Bridge (client)|l=arch}}
* {{intel|Ivy Bridge (client)|l=arch}}
* {{intel|Haswell (client)|l=arch}}
* {{intel|Broadwell (client)|l=arch}}
* {{intel|Skylake (client)|l=arch}}
* {{intel|Kaby Lake|l=arch}}
* {{intel|Coffee Lake|l=arch}}
* {{intel|Whiskey Lake|l=arch}}
* {{intel|Amber Lake|l=arch}}
* {{intel|Comet Lake|l=arch}}
* {{intel|Keystone Lake|l=arch}}
* {{intel|Rocket Lake|l=arch}}
* {{intel|Cannon Lake|l=arch}} ("Skymont")
* {{intel|Ice Lake (client)|l=arch}}
* {{intel|Tiger Lake|l=arch}}
* {{intel|Alder Lake|l=arch}}
* {{intel|Meteor Lake|l=arch}}
}}


{{collist
| count = 4
| style= margin-left: 20px;
|
'''Server SoC:'''
* {{intel|Core (server)|l=arch}}
* {{intel|Penryn (server)|l=arch}}
* {{intel|Nehalem (server)|l=arch}}
* {{intel|Westmere (server)|l=arch}}
* {{intel|Sandy Bridge (server)|l=arch}}
* {{intel|Ivy Bridge (server)|l=arch}}
* {{intel|Haswell (server)|l=arch}}
* {{intel|Broadwell (server)|l=arch}}
* {{intel|Skylake (server)|l=arch}}
* {{intel|Cascade Lake|l=arch}}
* {{intel|Cooper Lake|l=arch}}
* {{intel|Ice Lake (server)|l=arch}}
* {{intel|Sapphire Rapids|l=arch}}
* {{intel|Granite Rapids|l=arch}}
* {{intel|Diamond Rapids|l=arch}}
}}


{{collist
| count = 4
| style= margin-left: 20px;
|
'''Networking SoC:'''
* {{intel|Snow Ridge|l=arch}}
* {{intel|Tanner Ridge|l=arch}}
}}


{{collist
| count = 4
| style= margin-left: 20px;
|
'''High-Perf (Big Cores):'''
* {{intel|Palm Cove|l=arch}}
* {{intel|Sunny Cove|l=arch}}
* {{intel|Willow Cove|l=arch}}
* {{intel|Golden Cove|l=arch}}
* {{intel|Ocean Cove|l=arch}}
}}


{{collist
| count = 4
| style= margin-left: 20px;
|
'''High-Efficiency (Small Cores)'''
* {{intel|Bonnell|l=arch}}
* {{intel|Saltwell|l=arch}}
* {{intel|Silvermont|l=arch}}
* {{intel|Airmont|l=arch}}
* {{intel|Goldmont|l=arch}}
* {{intel|Goldmont Plus|l=arch}}
* {{intel|Tremont|l=arch}}
}}

'''MCU:'''
{{collist
| count = 1
|
* {{intel|Lakemont|l=arch}}
}}

'''ULP ([[ARM]]):'''
{{collist
| count = 3
|
* .. From [[DEC]]
* {{intel|XScale|l=arch}}
* {{intel|XScale 2|l=arch}}
* {{intel|XScale 3|l=arch}}
* {{intel|Mohawk|l=arch}}
* Continued by [[Marvell]] ..
}}


'''Server (EPIC) ([[Itanium]]):'''
{{collist
| count = 4
|
* {{intel|Merced|l=arch}}
* {{intel|McKinley|l=arch}}
* {{intel|Madison|l=arch}}
* {{intel|Deerfield|l=arch}}
* {{intel|Hondo|l=arch}}
* {{intel|Madison 9M|l=arch}}
* {{intel|Fanwood|l=arch}}
* {{intel|Montecito|l=arch}}
* {{intel|Chivano|l=arch}}
* {{intel|Millington|l=arch}}
* {{intel|Montvale|l=arch}}
* {{intel|Tukwila|l=arch}}
* {{intel|Dimona|l=arch}}
* {{intel|Poulson|l=arch}}
* {{intel|Kittson|l=arch}}
}}
'''[[Many-core]]:'''
{{collist
| count = 2
| style= margin-left: 20px;
|
'''Early Research:'''
* {{intel|Polaris|l=arch}}
* {{intel|Larrabee|l=arch}}
* {{intel|Rock Creek|l=arch}}
}}
{{clear}}
{{collist
| count = 3
| style= margin-left: 20px;
|
'''{{intel|MIC Architectures}}:'''
* {{intel|Knights Ferry|l=arch}} (Aubrey Isle)
* {{intel|Knights Corner|l=arch}} (Angel Isle)
* {{intel|Knights Landing|l=arch}}
* {{intel|Knights Mill|l=arch}}
* {{intel|Knights Hill|l=arch}}
* {{intel|Knights Peak|l=arch}}
}}
'''Heterogeneous:'''
{{collist
| count = 1
|
* {{intel|Lakefield|l=arch}}
* {{intel|Ryefield|l=arch}}
}}


'''GPU:'''
{{collist
| count = 3
| style= margin-left: 20px;
|
'''Integrated:'''
* {{intel|Gen1|l=arch}}
* {{intel|Gen2|l=arch}}
* {{intel|Gen3|l=arch}}
* {{intel|Gen3.5|l=arch}}
* {{intel|Gen4|l=arch}}
* {{intel|Gen5|l=arch}}
* {{intel|Gen5.75|l=arch}} ("Ironlake")
* {{intel|Gen6|l=arch}}
* {{intel|Gen7|l=arch}}
* {{intel|Gen7.5|l=arch}}
* {{intel|Gen8|l=arch}}
* {{intel|Gen9|l=arch}}
* {{intel|Gen9.5|l=arch}}
* {{intel|Gen10|l=arch}}
* {{intel|Gen11|l=arch}}
* {{intel|Gen12|l=arch}}
}}
{{clear}}
{{collist
| count = 1
| style= margin-left: 20px;
|
'''Discrete:'''
* {{intel|Arctic Sound|l=arch}}
* {{intel|Jupiter Sound|l=arch}}
}}

'''Artificial Intelligence:'''
{{collist
| count = 3
| style= margin-left: 20px;
|
'''Training:'''
* {{intel|Lake Crest|l=arch}}
* {{intel|Spring Crest|l=arch}}
}}
{{clear}}
{{collist
| count = 3
| style= margin-left: 20px;
|
'''Inference:'''
* {{intel|Spring Hill|l=arch}}
}}

== Other Chips ==
{{collist
| count = 1
|
'''Neuromorphic:'''
* {{intel|Loihi}}
'''Artificial Intelligence'''
* {{intel|ETANN}}
'''Quantum:'''
* {{intel|Surface-17}}
* {{intel|Tangle Lake}}
'''RAM:'''
* {{intel|3101}}
* {{intel|1103}}
}}

== Architectural Concepts ==
{{collist
| count = 1
|
* {{\\|Mesh Interconnect Architecture}}
* {{\\|Ring Interconnect Architecture}}
}}

== Other ==
{{collist
| count = 2
| width = 200px
|
* {{intel|iAPX}}
* {{intel|iRMX}}
* {{intel|iSBC}}
* {{intel|iSBX}}
}}

== Other topics ==
{{collist
| count = 2
|
* {{\\|CPUID}}
* {{\\|CNVi}}
* {{\\|Flexpoint}}
* {{\\|Frequency Behavior}}
* {{\\|Innovation Engine}} (IE)
* {{\\|Management Engine}} (ME)
* {{\\|Process-Architecture-Optimization}} (PAO)
* {{\\|Process Technology}}
* {{\\|Tick-Tock}}
}}

== Technologies ==
{{collist
| count = 2
|
* {{\\|Dynamic Tuning}}
* {{\\|Hyper Scaling}}
* {{\\|Speed Select Technology}} (SST)
* {{\\|Turbo Boost Technology}} (TBT)
* {{\\|Thermal Velocity Boost}} (TVB)
* {{\\|DL Boost}}
}}

== Packaging Technologies ==
{{collist
| count = 2
|
* {{\\|Foveros}}
* {{\\|EMIB}}
}}

== Documents ==
See {{\\|Documents}}.

[[Category:intel]]
company type	public +
founded	July 18, 1968 +
founded location	Mountain View, California +
founder	Gordon Moore +, Robert Noyce + and Andrew Grove +
full page name	intel +
headquarters	Santa Clara, California +
instance of	semiconductor company +
name	Intel +
website	http://www.intel.com +
wikidata id	Q248 +