Editing Talk:intel/microarchitectures/broadwell (client)

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== dubious intel statement on scheduler size ==

According to the Intel presentation slides, they have "Larger out-of-order scheduler" but what's not clear is what they meant by that. The ROB seems to remain at 192 entries. Scheduler is still at 60 entries. Or am I missing something? --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 16:20, 14 April 2016 (EDT)

=== Source for scheduler size increase ===

Intel source for the increase in scheduler from 60 to 64: https://intel.lanyonevents.com/sz15/connect/fileDownload/session/ECA57E7DBF19B1A610382EB5ABF2B651/SZ15_ARCS001_100_ENGf.pdf slide 21

Also the instruction queue is increased from 2x20 to 2x25, but [citation needed] I guess, can't find it anymore :) --[[Special:Contributions/195.241.129.245|195.241.129.245]] 01:39, 18 July 2016 (EDT)

: ah thanks! so it did increase to 64 entries. I will update the diagram accordingly. Intel sure doesn't make that info easy to come by. -[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 11:43, 18 July 2016 (EDT)

:: Another nugget confirming 25/thread instruction queue: http://news.mynavi.jp/photo/articles/2015/03/10/xeon/images/Photo013l.jpg
:: Thanks to belazeebub at http://www.realworldtech.com/forum/?threadid=159609&curpostid=159618 !