//var -s %a $str($chr(233),100)) , %b $encode(%a,m,1) , %c $encode(%a,m,2) , %d $decode(%b,m) vs $decode(%c,m) var -p %iv $regsubex(foo,$bvar(&secret_chat_digest,1-8),/(\d+)\s?/g,$chr(\t))

| {{\|AM2918}}<br />{{\|AM29LS18}} || Quad D register with standard and 3-state outputs || 16, 20 | {{\|AM2919}} || Quad D register with dual 3-state outputs || 20

:'''D''' - [[dual in-line package|DIP]] | {{\|7474}} || Dual Positive-Edge-Triggered D Flip-Flops; Preset, Clear and Complimentary Outputs

...is [[double-pumped]] at the 4th pipe stage using a [[dual edge-trigged]] [[flip-flop]], interleaving alternate data bits. This reduced the crossbar area by roug ...d₃₁ ... d₂₃ ... d₁₅ ... d₇ ... d₀</div></div></div>

{{title|Scan Flip-Flop (SFF)}}[[File:scan flip flop.svg|right|200px]] ...ter-slave based [[D flip-flop]]. In other words, a scan flip-flop is a [[D flip-flop]] that allows its input to come from an alternative source.

|extension 21=VT-d

|MA-MD_ACT_L||O-IOMEM-S||DRAM Channel A-D Activation Command |MA0-MD0_CKE[1:0]<br/>MA1-MD1_CKE[1:0]||O-IOMEM-S||DRAM Channel A-D DIMM 0-1 Clock Enable

the GMI links, C & D for the xGMI and I/O links, and all four layers ...sides. This also applies to Socket sTRX4 (where only the four channels A, D, E, and H are available), Socket sWRX8 (with a maximum of one DIMM per chan

|M_DQS_H/L[7:0]||B-IO-D||DRAM Differential Data Strobe |P_GPP_RXP/RXN[3:0]||I-PCIe-D||General Purpose External PCIe Receive Data Differential Pairs

|MA/MB/MC/MD_ADD[15:0]||DRAM Channel A-D Column/Row Address

* Only four of the eight DRAM channels A-H are usable, namely A, D, E, and H, connected to {{abbr|UMC}}2, 3, 4, and 5 on the IOD.<!--AMD-56515

|MA0-ML0_CLK_H/L<br/>MA1-ML1_CLK_H/L||O-IOMEM-D||DRAM Channel A-L DIMM 0/1 Differential Clock |MAA-MLA_DQS_H/L[9:0]||B-IOMEM-D||DRAM Channel A-L Subchannel A Data Strobes (x4 and x8) Differential Pair