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==== CPU changes ==== | ==== CPU changes ==== | ||
− | * | + | * Most general purpose ALU operations execute at up to 4 ops/cycle for 8, 32 and 64-bit registers. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle). |
− | * | + | * MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms. |
− | * Vector moves have throughput of 4 op/cycle ( | + | * ADC and SBB have throughput of 1 op/cycle, same as Haswell. |
+ | * Vector moves have throughput of 4 op/cycle (move elimination). | ||
* vPCMPGTx on the same register is recognized as a zeroing idiom (4 ops/cycle, no execution unit) like vpXORxx and vPSUBx zeroing. | * vPCMPGTx on the same register is recognized as a zeroing idiom (4 ops/cycle, no execution unit) like vpXORxx and vPSUBx zeroing. | ||
− | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5 | + | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4. |
− | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle | + | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle. |
* Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle. Lower latency SIMD FP-add unit on port 1 removed in favour of running all FP math on the FMA units. | * Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle. Lower latency SIMD FP-add unit on port 1 removed in favour of running all FP math on the FMA units. | ||
− | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle | + | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle. |
* Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | * Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | ||
* vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. | * vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. |
Facts about "Skylake (client) - Microarchitectures - Intel"
codename | Skylake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/skylake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |