From WikiChip
Goldmont Plus - Microarchitectures - Intel
< intel‎ | microarchitectures
Revision as of 20:19, 25 July 2017 by At32Hz (talk | contribs) (Created page with "{{intel title|Goldmont Plus|arch}} {{microarchitecture |atype=CPU |name=Goldmont |designer=Intel |manufacturer=Intel |introduction=August 30, 2016 |process=14 nm |cores=2 |co...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)


Edit Values
Goldmont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionAugust 30, 2016
Process14 nm
Core Configs2, 4, 8
Pipeline
TypeSuperscalar
SpeculativeYes
Reg RenamingYes
Stages12-14
Instructions
ISAIA-32, x86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache1 MiB/2 Cores
16-way set associative
Cores
Core NamesApollo Lake
Succession
Goldmont Plus
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/goldmont_plus&oldid=56342"
Facts about "Goldmont Plus - Microarchitectures - Intel"
RDF feed
codenameGoldmont +
core count2 +, 4 + and 8 +
designerIntel +
first launchedAugust 30, 2016 +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architectureIA-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont +
pipeline stages (max)14 +
pipeline stages (min)12 +
process14 nm (0.014 μm, 1.4e-5 mm) +