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| − | {{intel title|Goldmont|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Goldmont
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |introduction=August 30, 2016
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| − | |process=14 nm
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| − | |cores=2
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| − | |cores 2=4
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| − | |cores 3=8
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| − | |cores 4=12
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| − | |cores 5=16
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| − | |type=Superscalar
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |stages min=12
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| − | |stages max=14
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| − | |isa=x86-64
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| − | |extension=MOVBE
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| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4.1
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| − | |extension 8=SSE4.2
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| − | |extension 9=POPCNT
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| − | |extension 10=AES
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| − | |extension 11=PCLMUL
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| − | |extension 12=RDRND
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| − | |extension 13=XSAVE
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| − | |extension 14=XSAVEOPT
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| − | |extension 15=FSGSBASE
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| − | |extension 16=SHA
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| − | |l1i=32 KiB
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| − | |l1i per=Core
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| − | |l1i desc=8-way set associative
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| − | |l1d=24 KiB
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| − | |l1d per=Core
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| − | |l1d desc=6-way set associative
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| − | |l2=1-2 MiB
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| − | |l2 per=2 Cores
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| − | |l2 desc=16-way set associative
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| − | |core name=Apollo Lake
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| − | |core name 2=Denverton
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| − | |predecessor=Airmont
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| − | |predecessor link=intel/microarchitectures/airmont
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| − | |successor=Goldmont Plus
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| − | |successor link=intel/microarchitectures/goldmont plus
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| − | }}
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| − | '''Goldmont''' ('''GLM''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices. Goldmont-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. Goldmont superseded {{intel|Airmont}} in August of 2016. With Goldmont, Intel stopped targeting smartphones altogether, cancelling the related cores and SKUs.
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| − | [[File:Atom E3900 SoC Front.png|right|thumb|250px|Intel Atom E3900 SoC series]]
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| | | | |
| − | == Codenames ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Platform !! Core !! Target
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| − | |-
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| − | | || {{intel|Apollo Lake|l=core}} || Entry-level PCs, Tablets
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| − | |-
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| − | | || {{intel|Denverton|l=core}} || Ultra-low power servers, networking, storage, and IoT
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| − | |-
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| − | | || style="text-decoration: line-through;" | {{intel|Willow Trail|l=core}} || style="text-decoration: line-through;" | Lightweight Tablets & high-end smartphone
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| − | |- style="text-decoration: line-through;"
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| − | | {{intel|Morganfield|l=platform}} || {{intel|Broxton|l=core}} || Smartphone
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| − | |}
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| − |
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| − | == Process Technology ==
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| − | {{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
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| − | Goldmont-based chips are manufactured on Intel's [[14 nm process]].
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| − |
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| − | == Architecture ==
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| − | [[File:atom c3000 on a wafer.png|right|350px]]
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| − | === Key changes from {{intel|Airmont}} ===
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| − | * Pipeline
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| − | ** Compared to Airmont, Goldmont is a 3-issue core.
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| − | ** NOPs, MOVs and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle).
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| − | ** ADC, SBB have 0.5 op/cycle throughput, unchanged from Airmont.
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| − | ** INC, DEC, BTx, shift ops are not faster than on Airmont, 8-bit shifts are slightly slower (0.66 op/cycle instead of 1).
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| − | ** Rotate-through-carry (RCL, RCR) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~12).
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| − | ** 16- and 64-bit shift-double (SHLD, SHRD) throughput continues to be slow and is slightly slower (used to be ~10 cycles per op, now ~14) than on Airmont. (32-bit SHLD, SHRD are fast: 2-4 cycles).
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| − | ** Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles.
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| − | ** Bit scan (BSF, BSR) throughput improved from 10 to 8 cycles per op.
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| − | ** MUL throughput is better by 1 cycle (used to be 5/7 cycles for 32/64-bit mul, now 4/6).
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| − | ** DIV is more than twice as fast as Airmont, 13 cycles for most divides, 128-bit/64-bit are ~42 cycles.
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| − | ** PUSH to POP forwarding is improved.
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| − | ** REP MOVS streaming copy is twice as fast: now ~26 bytes/cycle.
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| − | ** REP STOS fill is not improved: ~9 bytes/cycle.
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| − | ** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput >2 op/cycle. This includes often used ops like adds and multiplies:
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| − | *** MULPS and MULPD have 4 cycle latency and 1 op/cycle throughput (used to have L5 and T0.5).
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| − | *** ADDPD has 3 cycle latency and 1 op/cycle throughput (used to have L4 and T0.5).
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| − | ** CRC32 instruction throughput improved from 6 cycles/op to 1 cycle/op, latency is halved from 6 to 3.
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| − | * Gen 9 GPUs
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| − | ** {{intel|HD Graphics 400}} '''→''' {{intel|HD Graphics 500}} (12 Execution Units, no change)
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| − | ** {{intel|HD Graphics 405}} '''→''' {{intel|HD Graphics 505}} (18 Execution Units, up from 16)
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| − |
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| − | ====New instructions ====
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| − | Goldmont introduced a number of {{x86|extensions|new instructions}}:
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| − |
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| − | * {{x86|RDSEED|<code>RDSEED</code>}} - Generates 16, 32 or 64 bit random numbers seeds ([[NIST SP 800-90B]] & [[NIST SP 800-90C]])
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| − | * {{x86|SMAP|<code>SMAP</code>}} - Supervisor Mode Access Prevention
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| − | * {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions
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| − | * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory
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| − | * {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory.
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| − | * {{x86|CLFLUSHOPT|<code>CLFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
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| − | * {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
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| − | * FS/GS base access
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| − |
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| − | === Block Diagram ===
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| − | {{empty section}}
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| − |
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| − | === Memory Hierarchy ===
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| − | * Cache
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| − | ** Hardware prefetchers
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| − | ** L1 Cache:
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| − | *** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
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| − | *** 24 KiB 6-way set associative data, 64 B line size
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| − | *** Per core
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| − | ** L2 Cache:
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| − | *** 1 MiB 16-way set associative, 64 B line size
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| − | *** Per 2 cores
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| − | *** 32B/cycle, 17 cycle latency
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| − | ** L3 Cache:
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| − | *** No level 3 cache
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| − | ** RAM
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| − | *** Maximum of 1 [[GiB]], 2 GiB, 4 GiB, 8 GiB
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| − | *** dual 32-bit channels, 1 or 2 ranks per channel
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| − |
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| − | === Multithreading ===
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| − | Goldmont, like {{\\|Airmont}} has no support for Intel Hyper-Threading Technology.
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| − |
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| − | == Die Shot ==
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| − | Intel {{intel|Atom}} E3900 SoC series:
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| − | :[[File:atom e3900 die shot.jpg|650px]]
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| − |
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| − | == All Goldmont Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | <table class="wikitable sortable">
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| − | <tr><th colspan="12" style="background:#D6D6FF;">Goldmont Chips</th></tr>
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| − | <tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
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| − | <tr><th>Model</th><th>Family</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
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| − | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Goldmont]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?platform
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| − | |?core name
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| − | |?first launched
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| − | |?sdp
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| − | |?tdp
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| − | |?base frequency
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| − | |?max memory
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?integrated gpu max frequency
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| − | |format=template
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| − | |template=proc table 2
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| − | |userparam=13
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| − | |mainlabel=-
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| − | }}
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| − | {{table count|col=12|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Goldmont]]}}
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| − | </table>
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