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Difference between revisions of "arm holdings/microarchitectures/cortex-a5"
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|manufacturer=TSMC | |manufacturer=TSMC | ||
|introduction=October 22, 2009 | |introduction=October 22, 2009 | ||
| + | |isa=ARMv7 | ||
|predecessor=Cortex-A9 | |predecessor=Cortex-A9 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a9 | |predecessor link=arm_holdings/microarchitectures/cortex-a9 | ||
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* New [[in-order]] pipeline (form [[out-of-order]]) | * New [[in-order]] pipeline (form [[out-of-order]]) | ||
** Shorter [[pipeline]] (8, up from 9-12) | ** Shorter [[pipeline]] (8, up from 9-12) | ||
| + | *** 0.5x frequency (1 GHz, down from 2 GHz) | ||
** Single-issue (from [[dual-issue]]) | ** Single-issue (from [[dual-issue]]) | ||
* Reduced return stack size (4 entries, down from 8) | * Reduced return stack size (4 entries, down from 8) | ||
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** Hardware [[Fused Multiply-Accumulate]] | ** Hardware [[Fused Multiply-Accumulate]] | ||
* [[VFPv4]] (from [[VFPv3]]) | * [[VFPv4]] (from [[VFPv3]]) | ||
| + | * Memory subsystem | ||
| + | ** Level 1 [[instruction cache]] reduced to 2-way set associative (down from 4-way) | ||
{{expand list}} | {{expand list}} | ||
Latest revision as of 14:25, 31 December 2018
| Edit Values | |
| Cortex-A5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | October 22, 2009 |
| Instructions | |
| ISA | ARMv7 |
| Succession | |
Cortex-A5 (codename Sparrow) is the successor to the Cortex-A9, an ultra-low power ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Contents
Architecture[edit]
Key changes from Cortex-A9[edit]
- New in-order pipeline (form out-of-order)
- Shorter pipeline (8, up from 9-12)
- 0.5x frequency (1 GHz, down from 2 GHz)
- Single-issue (from dual-issue)
- Shorter pipeline (8, up from 9-12)
- Reduced return stack size (4 entries, down from 8)
- Integer
- Hardware Fused Multiply-Accumulate
- VFPv4 (from VFPv3)
- Memory subsystem
- Level 1 instruction cache reduced to 2-way set associative (down from 4-way)
This list is incomplete; you can help by expanding it.
Block Diagram[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Licensees[edit]
Arm named the following companies as licensees.
Facts about "Cortex-A5 - Microarchitectures - ARM"
| codename | Cortex-A5 + |
| designer | ARM Holdings + |
| first launched | October 22, 2009 + |
| full page name | arm holdings/microarchitectures/cortex-a5 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A5 + |
