From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a5"
< arm holdings

(Key changes from {{\\|Cortex-A9}})
(Key changes from {{\\|Cortex-A9}})
Line 17: Line 17:
 
* New [[in-order]] pipeline (form [[out-of-order]])
 
* New [[in-order]] pipeline (form [[out-of-order]])
 
** Shorter [[pipeline]] (8, up from 9-12)
 
** Shorter [[pipeline]] (8, up from 9-12)
 +
*** 0.5x frequency (1 GHz, down from 2 GHz)
 
** Single-issue (from [[dual-issue]])
 
** Single-issue (from [[dual-issue]])
 
* Reduced return stack size (4 entries, down from 8)
 
* Reduced return stack size (4 entries, down from 8)

Revision as of 00:37, 31 December 2018

Edit Values
Cortex-A5 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 22, 2009
Succession

Cortex-A5 (codename Sparrow) is the successor to the Cortex-A9, an ultra-low power ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Architecture

Key changes from Cortex-A9

This list is incomplete; you can help by expanding it.

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees

Arm named the following companies as licensees.

codenameCortex-A5 +
designerARM Holdings +
first launchedOctober 22, 2009 +
full page namearm holdings/microarchitectures/cortex-a5 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A5 +