Difference between revisions of "intel/core i5/i5-6360u"

	Edit Values
	Core i5-6360U
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	i5-6360U
Part Number	FJ8066202499208
S-Spec	SR2JM
Market	Mobile
Introduction	September 1, 2015 (announced); September 27, 2015 (launched)
Release Price	$304.00
Shop	Amazon
	General Specs
Family	Core i5
Series	i5-6000
Locked	Yes
Frequency	2,000 MHz
Turbo Frequency	3,100 MHz (1 core),; 2,900 MHz (2 cores)
Bus type	OPI
Bus rate	4 GT/s
Clock multiplier	20
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake
Core Name	Skylake U
Core Family	6
Core Model	78
Core Stepping	K1
Process	14 nm
Technology	CMOS
MCP	Yes (3 dies)
Word Size	64 bit
Cores	2
Threads	4
Max Memory	32 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	0.55 V-1.52 V
TDP	15 W
cTDP down	9.5 W
Tjunction	0 °C – 100 °C
Tstorage	-25 °C – 125 °C
	Packaging
Package	FCBGA-1356 (BGA)
Dimension	42 mm x 24 mm x 1.3 mm
Pitch	0.65 mm
Ball Count	1356
Ball Comp	SAC405
Interconnect	BGA-1356

Latest revision as of 15:20, 13 December 2017

Core i5-6360U is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.0 GHz with a turbo boost of up to 3.1 GHz. The i5-6360U has a TDP of 15 W with a configurable TDP-down of 9.5 W. This chip incorporates the Iris Graphics 540 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6360U comes with an additional 64 MiB of embedded DRAM side cache.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

128 KiB

131,072 B
0.125 MiB

L1I$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	4-way set associative	write-back

L3$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		2x2 MiB		write-back

L4$

64 MiB

65,536 KiB
67,108,864 B
0.0625 GiB

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2133, LPDDR3-1866, DDR3L-1600
Supports ECC	No
Max Mem	32 GiB
Controllers	1
Channels	2
Max Bandwidth	31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s
Bandwidth	Single 15.89 GiB/s Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	12
Configs	1x4, 2x2, 1x2+2x1, 4x1

Graphics[edit]

The Iris Graphics 540 includes 64 MiB of side eDRAM cache in addition to everything else.

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Iris Graphics 540

Designer

Intel

Device ID

0x1926

Execution Units

48

Max Displays

3

Max Memory

32 GiB

32,768 MiB
33,554,432 KiB
34,359,738,368 B

Frequency

300 MHz

0.3 GHz
300,000 KHz

Burst Frequency

1,000 MHz

1 GHz
1,000,000 KHz

Output

DP, eDP, HDMI, DVI

Max Resolution

HDMI	4096x2304 @24 Hz
DP	4096x2304 @60 Hz
eDP	4096x2304 @60 Hz

Standards

DirectX	12
OpenGL	4.4
OpenCL	2.0
DP	1.2
eDP	1.3
HDMI	1.4a

Additional Features

Intel Quick Sync Video

Intel InTru 3D

Intel Clear Video

Intel Clear Video HD

[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities
Codec	Encode			Decode
Codec	Profiles	Levels	Max Resolution	Profiles	Levels	Max Resolution
MPEG-2 (H.262)	Main	High	1080p (FHD)	Main	Main, High	1080p (FHD)
MPEG-4 AVC (H.264)	High, Main	5.1	2160p (4K)	Main, High, SHP, MHP	5.1	2160p (4K)
JPEG/MJPEG	Baseline	-	16k x 16k	Baseline	Unified	16k x 16k
HEVC (H.265)	Main	5.1	2160p (4K)	Main, Main 10	5.1	2160p (4K)
VC-1	✘			Advanced, Main, Simple	3, High	3840x3840
VP8	Unified	Unified	-	0	Unified	1080p
VP9	✘			0	Unified	2160p (4K)

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
SGX	Software Guard Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
Flex Memory	Flex Memory Access
ISRT	Smart Response Technology
MWT	My WiFi Technology
SIPP	Stable Image Platform Program
IPT	Identity Protection Technology

@@ Line 1: / Line 1: @@
 {{intel title|Core i5-6360U}}
-{{mpu
+{{chip
 |name=Core i5-6360U
 |image=skylake u (front; iris).png
@@ Line 47: / Line 47: @@
 |package module 1={{packages/intel/fcbga-1356}}
 }}
-'''Core i5-6360U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.0 GHz with a {{intel|turbo boost}} of up to 3.1 GHz. The i5-6360U has a TDP of 15 W with a configurable-down TDP of 9.5 W. This chip incorporates the {{intel|Iris Graphics 540}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6360U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
+'''Core i5-6360U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.0 GHz with a {{intel|turbo boost}} of up to 3.1 GHz. The i5-6360U has a TDP of 15 W with a configurable TDP-down of 9.5 W. This chip incorporates the {{intel|Iris Graphics 540}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6360U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
 == Cache ==
@@ Line 162: / Line 162: @@
 |avx=Yes
 |avx2=Yes
-|avx512=No
 |abm=Yes
 |tbm=No

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i5-6360U - Intel#package + and Core i5-6360U - Intel#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus type	OPI +
clock multiplier	20 +
core count	2 +
core family	6 +
core model	78 +
core name	Skylake U +
core stepping	K1 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
device id	0x1926 +
die count	3 +
family	Core i5 +
first announced	September 1, 2015 +
first launched	September 27, 2015 +
full page name	intel/core i5/i5-6360u +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Stable Image Platform Program + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel stable image platform program support	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	Iris Graphics 540 +
integrated gpu base frequency	300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	48 +
integrated gpu max frequency	1,000 MHz (1 GHz, 1,000,000 KHz) +
integrated gpu max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l4$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	September 27, 2015 +
main image	+
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	12 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i5-6360U +
name	Core i5-6360U +
package	FCBGA-1356 +
part number	FJ8066202499208 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 304.00 (€ 273.60, £ 246.24, ¥ 31,412.32) +
s-spec	SR2JM +
series	i5-6000 +
smp max ways	1 +
supported memory type	DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 +
tdp	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp down	9.5 W (9,500 mW, 0.0127 hp, 0.0095 kW) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (2 cores)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

WikiChip

The Fuse Coverage

Social Media

Companies

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Technology Nodes

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Cavium

Samsung

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AMD

Ampere

Apple

Cavium

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NXP

Qualcomm

Renesas

Samsung

Latest revision as of 15:20, 13 December 2017

Contents

Cache[edit]

Memory controller[edit]

Expansions[edit]

Graphics[edit]

Features[edit]