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Difference between revisions of "amd/k6-2/k6-2-300bnz-66"
< amd‎ | k6-2

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{{amd title|AMD-K6-2/300BNZ-66}}
 
{{amd title|AMD-K6-2/300BNZ-66}}
{{mpu
+
{{chip
 
| name                = K6-2/300BNZ-66
 
| name                = K6-2/300BNZ-66
 
| no image            = No
 
| no image            = No
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| model number        = K6-2/300BNZ-66
 
| model number        = K6-2/300BNZ-66
 
| part number        = AMD-K6-2/300BNZ-66
 
| part number        = AMD-K6-2/300BNZ-66
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = March 22, 1999
 
| first announced    = March 22, 1999
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| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
| electrical          = Yes
+
 
 
| power              = 10 W
 
| power              = 10 W
 
| v core              = 1.8 V
 
| v core              = 1.8 V
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== Features ==
 
== Features ==
{{mpu features
+
{{x86 features
 
| mmx  = true
 
| mmx  = true
 
| 3dnow = true
 
| 3dnow = true

Latest revision as of 16:08, 13 December 2017

Edit Values
K6-2/300BNZ-66
General Info
DesignerAMD
ManufacturerAMD
Model NumberK6-2/300BNZ-66
Part NumberAMD-K6-2/300BNZ-66
MarketMobile
IntroductionMarch 22, 1999 (announced)
March 22, 1999 (launched)
ShopAmazon
General Specs
FamilyK6-2
SeriesK6-2 Mobile
Frequency299.99 MHz
Bus typeFSB
Bus speed66.66 MHz
Bus rate66.66 MT/s
Clock multiplier4.5
CPUID58C
Microarchitecture
MicroarchitectureK6-2
PlatformSuper 7
Core NameChomper Extended
Core Family5
Core Model8
Core Stepping12
Process0.25 µm
Transistors9,300,000
TechnologyCMOS
Die81 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation10 W
Vcore1.8 V ± 0.1 V
VI/O3.3675 V ± 7%
Tcase0 °C – 85 °C
Tstorage-65 °C – 150 °C

K6-2/300BNZ-66 was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 66 MHz.

Cache[edit]

Main article: K6-2 § Cache

L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

  • Auto-power down state
  • Stop clock state

Documents[edit]

DataSheet[edit]

l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +