Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/k6-2/k6-2e-333afr"
m (Bot: corrected param) |
m (Bot: replacing deprecated (and now obselete) {{mpu features}} with {{x86 features}}) |
||
| Line 104: | Line 104: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = true | | mmx = true | ||
| 3dnow = true | | 3dnow = true | ||
Revision as of 15:44, 13 December 2017
Template:mpu K6-2/337AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 333 MHz and had a FSB operating at 95 MHz.
Contents
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|||
|
||||
- Auto-power down state
- Stop clock state
Documents
DataSheet
- AMD-K6-2E Processor Data Sheet; Publication #22529 Revision B/0, January 2000
Facts about "K6-2E/333AFR - AMD"
| l1d$ description | 2-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |