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Difference between revisions of "amd/k6-2/k6-2-300bnz"
< amd‎ | k6-2

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| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
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| electrical          = Yes
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| power              = 10 W
 
| power              = 10 W
 
| v core              = 1.8 V
 
| v core              = 1.8 V

Revision as of 21:53, 23 June 2017

Template:mpu K6-2/300BNZ was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 100 MHz.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state

Documents

DataSheet

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-2/k6-2-300bnz&oldid=47221"
Facts about "AMD-K6-2/300BNZ - AMD"
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l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +