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Difference between revisions of "amd/duron/dhm0850avs1bm"
< amd‎ | duron

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| bus speed          = 100 MHz
 
| bus speed          = 100 MHz
 
| bus rate            = 200 MT/s
 
| bus rate            = 200 MT/s
| clock multiplier    = 8
+
| clock multiplier    = 8.5
 
| cpuid              = 660
 
| cpuid              = 660
  
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| socket 0 type      = PGA-462
 
| socket 0 type      = PGA-462
 
}}
 
}}
 +
The '''Mobile Duron 850''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 850 MHz with a bus capable of 200 MT/s. This particular model (the DHM0850AVS1BM) is sometimes labeled by AMD as {{amd|Athlon}} but is shipped as Duron due to defective or disabled cache. This chip has a core model of "6" instead of "7" unlike the rest of the {{amd|Camaro|l=core}} models.
  
 
== Cache ==
 
== Cache ==

Revision as of 16:38, 24 October 2016

Template:mpu The Mobile Duron 850 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 850 MHz with a bus capable of 200 MT/s. This particular model (the DHM0850AVS1BM) is sometimes labeled by AMD as Athlon but is shipped as Duron due to defective or disabled cache. This chip has a core model of "6" instead of "7" unlike the rest of the Camaro models.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State

See also

has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +