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Difference between revisions of "amd/k6-2/k6-2-500ahx"
< amd‎ | k6-2

Line 28: Line 28:
 
| clock multiplier    = 5
 
| clock multiplier    = 5
 
| cpuid              = 58C
 
| cpuid              = 58C
 +
 +
| microarch          = K6-2
 +
| platform            = Super 7
 +
| chipset            =
 +
| core name          = Chomper Extended
 +
| core family        = 5
 +
| core model          = 8
 +
| core stepping      = 12
 +
| process            = 0.25 µm
 +
| transistors        = 9,300,000
 +
| technology          = CMOS
 +
| die size            = 81 mm²
 +
| word size          = 32 bit
 +
| core count          = 1
 +
| thread count        = 1
 +
| max cpus            = 1
 +
| max memory          = 4 GB
 
}}
 
}}
 
'''K6-2/500AHX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 500 MHz with a [[FSB]] of 100 MHz consumed 31.3 W.
 
'''K6-2/500AHX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 500 MHz with a [[FSB]] of 100 MHz consumed 31.3 W.

Revision as of 21:09, 3 August 2016

Template:mpu K6-2/500AHX was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 500 MHz with a FSB of 100 MHz consumed 31.3 W.