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Difference between revisions of "65 nm lithography process"

(65 nm Microprocessors)
(Industry)
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| 0.570 µm<sup>2</sup> || 0.57x || 0.65 µm<sup>2</sup> || 0.65x || 0.49 µm<sup>2</sup> || || || || || || ||
 
| 0.570 µm<sup>2</sup> || 0.57x || 0.65 µm<sup>2</sup> || 0.65x || 0.49 µm<sup>2</sup> || || || || || || ||
 
|-
 
|-
| 0.680 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> || || 0.490 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> || || || || ? µm<sup>2</sup> || ?x
+
| 0.680 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> || || 0.490 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> || || 0.525 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
 
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=== Design Rules ===
 
=== Design Rules ===

Revision as of 11:09, 25 April 2016

The 65 nm lithography process is a full node semiconductor manufacturing process following the 80 nm process stopgap. Commercial integrated circuit manufacturing using 65 nm process began in 2005. This technology was superseded by the 55 nm process (HN) / 45 nm process (FN) in 2007.

Industry

Fab
Process Name​
1st Production​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (LP)
Intel IBM / Toshiba / Sony / AMD TI IBM / Chartered / Infineon / Samsung TSMC Fujitsu
P1264 CS-200/CS-201/CS-250
2005 2005 2007 2005 2005 2006
Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ Value 90 nm Δ
220 nm 0.85x 250 nm  ?x  ? nm  ?x 200 nm 0.82x 160 nm 0.67x  ? nm  ?x
210 nm 0.95x  ? nm  ?x  ? nm  ?x 180 nm 0.73 180 nm 0.75x  ? nm  ?x
0.570 µm2 0.57x 0.65 µm2 0.65x 0.49 µm2
0.680 µm2 0.540 µm2 0.490 µm2 0.540 µm2 0.525 µm2  ?x  ? µm2  ?x

Design Rules

65 nm Microprocessors

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65 nm System on Chips

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65 nm Microarchitectures

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