Difference between revisions of "65 nm lithography process"

Revision as of 04:32, 24 April 2016

Semiconductor lithography processes technology

The 65 nm lithography process is a full node semiconductor manufacturing process following the 80 nm process stopgap. Commercial integrated circuit manufacturing using 65 nm process began in 2006. This technology was superseded by the 55 nm process (HN) / 45 nm process (FN) in 2007.

Industry

Fab

Contacted Gate Pitch
Interconnect Pitch (M1P)
SRAM bit cell (HD)
SRAM bit cell (LP)

Intel		IBM / Toshiba / Sony / AMD		TI		IBM / Chartered / Infineon / Samsung
Value	90 nm Δ	Value	90 nm Δ	Value	90 nm Δ	Value	90 nm Δ
220 nm	0.85x	250 nm	?x	? nm	?x	200 nm	0.82
210 nm	0.95x	? nm	?x	? nm	?x	180 nm	0.73
0.570 µm²	0.57x	0.65 µm²	0.65x	0.49 µm²
0.680 µm²		0.540 µm²		0.490 µm²		0.540 µm²

Design Rules

Intel 65nm Design Rules
Layer	Pitch	Thick	Aspect Ratio
Isolation	220 nm	320 nm	-
Polysilicon	220 nm	90 nm	-
Contacted Gate	220 nm		-
Metal 1	210 nm	170 nm	1.6
Metal 2	210 nm	190 nm	1.8
Metal 3	220 nm	200 nm	1.8
Metal 4	280 nm	250 nm	1.8
Metal 5	330 nm	300 nm	1.8
Metal 6	480 nm	430 nm	1.8
Metal 7	720 nm	650 nm	1.8
Metal 8	1.80 µm	975 nm	1.8

65 nm Microprocessors

This list is incomplete; you can help by expanding it.

65 nm System on Chips

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65 nm Microarchitectures

Intel
- Core

This list is incomplete; you can help by expanding it.

@@ Line 3: / Line 3: @@
 == Industry ==
+{{scrolling table/top|style=text-align: right; | first=Fab
-=== Intel ===
+ |&nbsp;
-{| class="wikitable"
+ |Contacted Gate Pitch
+ |Interconnect Pitch (M1P)
+ |SRAM bit cell (HD)
+ |SRAM bit cell (LP)
+}}
+{{scrolling table/mid}}
 |-
-| || Measurement || Scaling from [[90 nm]]
+! colspan="2" | [[Intel]] !! colspan="2" | [[IBM]] / [[Toshiba]] / [[Sony]] / [[AMD]] !! colspan="2" | [[TI]] !! colspan="2" | [[IBM]] / [[Chartered]] / [[Infineon]] / [[Samsung]]
 |-
-| Contacted Gate Pitch || 220 nm || 0.85x
+! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ !! Value !! [[90 nm]] Δ
 |-
-| Interconnect Pitch (M1P) || 210 nm || 0.95x
+| 220 nm || 0.85x || 250 nm || ?x || ? nm || ?x || 200 nm || 0.82
 |-
-| [[SRAM]] bit cell || 0.570 µm<sup>2</sup> || 0.57x
+| 210 nm || 0.95x || ? nm || ?x || ? nm || ?x || 180 nm  || 0.73
-|}
-{| class="wikitable"
 |-
-! colspan="4" | Design Rules
+| 0.570 µm<sup>2</sup> || 0.57x || 0.65 µm<sup>2</sup> || 0.65x || 0.49 µm<sup>2</sup> || || ||
+|-
+| 0.680 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> || || 0.490 µm<sup>2</sup> || || 0.540 µm<sup>2</sup> ||
+{{scrolling table/end}}
+=== Design Rules ===
+{| class="wikitable collapsible collapsed"
+|-
+! colspan="4" | Intel 65nm Design Rules
 |-
 ! Layer !! Pitch !! Thick !! Aspect Ratio

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Revision as of 04:32, 24 April 2016

Contents

Industry

Design Rules

65 nm Microprocessors

65 nm System on Chips

65 nm Microarchitectures