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Latest revision | Your text | ||
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|stages max=19 | |stages max=19 | ||
|isa=x86-64 | |isa=x86-64 | ||
+ | |extension=MOVBE | ||
|extension 2=MMX | |extension 2=MMX | ||
|extension 3=SSE | |extension 3=SSE | ||
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|extension 22=TXT | |extension 22=TXT | ||
|extension 23=TSX | |extension 23=TSX | ||
+ | |extension 24=RDSEED | ||
|extension 25=ADCX | |extension 25=ADCX | ||
+ | |extension 26=PREFETCHW | ||
|extension 27=CLFLUSHOPT | |extension 27=CLFLUSHOPT | ||
|extension 28=XSAVE | |extension 28=XSAVE | ||
+ | |extension 29=SGX | ||
+ | |extension 30=MPX | ||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
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**** {{intel|Skylake Y|l=core}} and Skylake U cores have chipset in the same package (simplified {{intel|on Package I/O|OPIO}}) | **** {{intel|Skylake Y|l=core}} and Skylake U cores have chipset in the same package (simplified {{intel|on Package I/O|OPIO}}) | ||
**** Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane | **** Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane | ||
− | **** Limits motherboard trace design to 7 inches max from | + | **** Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset |
** PCIe & DMI upgraded to Gen3 | ** PCIe & DMI upgraded to Gen3 | ||
** More I/O (configurable as PCIe/SATA/USB3) | ** More I/O (configurable as PCIe/SATA/USB3) | ||
** Lower-power I/O (eMMC, UFS, SDXC) | ** Lower-power I/O (eMMC, UFS, SDXC) | ||
** CSI-2 for the integrated IPU (mobile SKUs) | ** CSI-2 for the integrated IPU (mobile SKUs) | ||
− | ** Intel Sensor Solution Hub | + | ** Intel Sensor Solution Hub integrationLarger Line Fill Buffer? |
− | |||
* [[System Agent]] | * [[System Agent]] | ||
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* Core | * Core | ||
** Front End | ** Front End | ||
+ | *** Larger legacy pipeline delivery (5 µOPs, up from 4) | ||
+ | **** Another simple decoder has been added. | ||
*** Allocation Queue (IDQ) | *** Allocation Queue (IDQ) | ||
− | |||
**** Larger delivery (6 µOPs, up from 4) | **** Larger delivery (6 µOPs, up from 4) | ||
**** 2.28x larger buffer (64/thread, up from 56) | **** 2.28x larger buffer (64/thread, up from 56) | ||
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** Direct X 12, OpenCL 2.0, OpenGL 4.4 | ** Direct X 12, OpenCL 2.0, OpenGL 4.4 | ||
** Up to 24 EUs GT2 (same as {{\\|Haswell}}); 48 EUs for GT3, and up to 72 EUs on {{intel|Iris Pro Graphics}} | ** Up to 24 EUs GT2 (same as {{\\|Haswell}}); 48 EUs for GT3, and up to 72 EUs on {{intel|Iris Pro Graphics}} | ||
− | *** | + | *** 1,152 GFLOPS @ 1 GHz |
==== CPU changes ==== | ==== CPU changes ==== | ||
− | * | + | * Most general purpose ALU operations execute at up to 4 ops/cycle for 8, 32 and 64-bit registers. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle). |
− | * | + | * MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms. |
− | * Vector moves have throughput of 4 op/cycle ( | + | * ADC and SBB have throughput of 1 op/cycle, same as Haswell. |
− | * | + | * Vector moves have throughput of 4 op/cycle (move elimination). |
− | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5 | + | * Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle. |
− | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle | + | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4. |
− | * Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle | + | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle. |
− | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle | + | * Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle. |
+ | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle. | ||
* Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | * Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | ||
* vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. | * vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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The Skylake [[system on a chip]] consists of a five major components: CPU core, [[last level cache|LLC]], Ring interconnect, System agent, and the [[integrated graphics]]. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. [[superset]] of features). Skylake features an improved core (see [[#Pipeline|§ Pipeline]]) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically [[dual-core]] while mainstream desktop models are typically [[quad-core]] with dual-core desktop models still offered for value models (e.g. {{intel|Celeron}}). Accompanying the cores is the LCC ([[last level cache]] or [[L3$]] as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth. | The Skylake [[system on a chip]] consists of a five major components: CPU core, [[last level cache|LLC]], Ring interconnect, System agent, and the [[integrated graphics]]. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. [[superset]] of features). Skylake features an improved core (see [[#Pipeline|§ Pipeline]]) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically [[dual-core]] while mainstream desktop models are typically [[quad-core]] with dual-core desktop models still offered for value models (e.g. {{intel|Celeron}}). Accompanying the cores is the LCC ([[last level cache]] or [[L3$]] as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth. | ||
− | Accompanying the cores is the {{\\|Gen9}} [[integrated graphics]] unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 ({{\\|gen9#Scalability|Gen9 § Pipeline}}) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated [[eDRAM]] ranging from 64 to | + | Accompanying the cores is the {{\\|Gen9}} [[integrated graphics]] unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 ({{\\|gen9#Scalability|Gen9 § Pipeline}}) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated [[eDRAM]] ranging from 64 GiB to 120 GiB in capacity. The eDRAM is packaged along with the SoC in the same package. |
On the other side is the {{intel|System Agent}} (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded [[integrated memory controller]] (IMC) with most mainstream models supporting faster memory and dual-channel [[DDR4]]. The SA in Skylake also includes the [[Display Controller]] which now supports higher resolution displays with up to three displays for all mainstream models. | On the other side is the {{intel|System Agent}} (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded [[integrated memory controller]] (IMC) with most mainstream models supporting faster memory and dual-channel [[DDR4]]. The SA in Skylake also includes the [[Display Controller]] which now supports higher resolution displays with up to three displays for all mainstream models. | ||
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===== Decoding ===== | ===== Decoding ===== | ||
[[File:skylake decode.svg|right|425px]] | [[File:skylake decode.svg|right|425px]] | ||
− | Up to | + | Up to five (3 + 2 fused or up to 5 unfused) pre-decoded instructions are sent to the decoders each cycle. Like the fetchers, the Decoders alternate between the two thread each cycle. Decoders read in [[macro-operations]] and emit regular, fixed length [[µOPs]]. Skylake represents a big genealogical change from the last couple of microarchitectures. Skylake's pipeline is wider than it predecessors; Skylake adds another [[simple decoder]]. The five decoders are asymmetric; the first one, Decoder 0, is a [[complex decoder]] while the other four are [[simple decoders]]. A simple decoder is capable of translating instructions that emit a single fused-[[µOP]]. By contrast, a [[complex decoder]] can decode anywhere from one to four fused-µOPs. Skylake is now capable of decoding 5 macro-ops per cycle or 25% more than {{\\|Broadwell}}, however this does not translates directly to direct IPC uplift due to various other more restricting points in the pipeline. Intel chose not to increase the number of complex decoders because it's much harder to extract additional parallelism from the µOPs emitted by a complex instruction. Overall up to 5 simple instructions can be decoded each cycle with lesser amounts if the complex decoder needs to emit addition µOPs; i.e., for each additional µOP the complex decoder needs to emit, 1 less simple decoder can operate. In other words, for each additional µOP the complex decoder emits, one less decoder is active. |
====== MSROM & Stack Engine ====== | ====== MSROM & Stack Engine ====== | ||
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Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | ||
− | Information from the new domains, including additional thermal | + | Information from the new domains, including additional thermal skin temperature control information is now supplied to OEMs. |
==== Power of System (Psys) ==== | ==== Power of System (Psys) ==== | ||
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The IPU hardware supports: | The IPU hardware supports: | ||
− | + | * 13 [[megapixel|MP]] zero [[shutter lag]] 1080p60/2160p30 video capture and imaging and a large array of standardized image processing capabilities. | |
− | |||
* Face detection and recognition (smile/blink/group setting) | * Face detection and recognition (smile/blink/group setting) | ||
* Full resolution still capture during video captures | * Full resolution still capture during video captures | ||
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* 2-cores group: | * 2-cores group: | ||
− | + | * ~8.91 mm x ~2.845 mm | |
− | + | * ~25.347 mm² | |
: [[File:skylake 2x core complex die.png|500px]] | : [[File:skylake 2x core complex die.png|500px]] | ||
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* 4-core group | * 4-core group | ||
− | + | * ~8.844 mm x 5.694 mm | |
− | + | * ~50.354 mm² | |
: [[File:skylake 4x core complex die.png|500px]] | : [[File:skylake 4x core complex die.png|500px]] | ||
+ | |||
=== Integrated Graphics === | === Integrated Graphics === |
Facts about "Skylake (client) - Microarchitectures - Intel"
codename | Skylake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/skylake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |