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File:ibm stacked silicon nanowire transistors.jpg

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Summary[edit]

Stacked silicon nanowire transistors. Image by IBM. 

Pictured: a scan of IBM Research Alliance’s 5nm transistor, built using an industry-first process to stack silicon nanosheets as the device structure – achieving a scale of 30 billion switches on a fingernail-sized chip that will deliver significant power and performance enhancements over today’s state-of-the-art 10nm chips. (Credit: IBM)

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current09:59, 5 June 2017Thumbnail for version as of 09:59, 5 June 20171,164 × 570 (409 KB)At32Hz (talk | contribs)Stacked silicon nanowire transistors.
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Metadata

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Orientation Normal
Horizontal resolution 59 dpi
Vertical resolution 59 dpi
Software used Adobe Photoshop Elements 8.0 Windows
File change date and time 23:18, 4 June 2017
Color space sRGB
Image width 1,164 px
Image height 570 px
Date and time of digitizing 19:18, 4 June 2017
Date metadata was last modified 19:18, 4 June 2017
Unique ID of original document xmp.did:3BB6C8F49A49E7118F4CD13684C894B9
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