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Latest revision Your text
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* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
 
* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
 
* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
 
* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
* '''Mem:''' Up 64 GiB of dual-channel 2133 MT/s DDR4
+
* '''Mem:''' Up 64 GiB of dual-channel 2311 MT/s DDR4
  
 
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designerZhaoxin + and VIA Technologies +
first announced2016 +
first launched2016 +
full page namezhaoxin/kaixian +
instance ofmicroprocessor family +
instruction set architecturex86 +
main designerZhaoxin +
manufacturerTSMC + and HLMC +
microarchitectureIsaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +
nameKaiXian +
process40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +