From WikiChip
Difference between revisions of "xiaomi/surge/s2"
< xiaomi‎ | surge

Line 43: Line 43:
 
| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  
| process            = 28 nm
+
| process            = 10 nm
 
| transistors        =  
 
| transistors        =  
 
| technology          = CMOS
 
| technology          = CMOS
Line 96: Line 96:
 
}}
 
}}
  
'''Surge S2''' is a {{arch|64}} [[octa-core]] performance [[ARM]] system-on-chip designed by [[Xiaomi]] set to be introduced in late [[2017]]. The Surge S2 is Xiaomi flagship processor. This chip incorporates eight cores in a {{armh|big.LITTLE}} configuration with four high-performance {{armh|Cortex-A73}} cores operating at up to 2.7 GHz with another four low-power {{armh|Cortex-A53}} cores operating at 2 GHz. This processor is fabricated on TSMC's [[28 nm process|28 nm HPC+ process]] and incorporates a {{armh|Mali-G71}} [[IGP]].
+
'''Surge S2''' is a {{arch|64}} [[octa-core]] performance [[ARM]] system-on-chip designed by [[Xiaomi]] set to be introduced in late [[2017]]. The Surge S2 is Xiaomi flagship processor. This chip incorporates eight cores in a {{armh|big.LITTLE}} configuration with four high-performance {{armh|Cortex-A73}} cores operating at up to 2.7 GHz with another four low-power {{armh|Cortex-A53}} cores operating at 2 GHz. This processor is fabricated on TSMC's [[10 nm process]] and incorporates a {{armh|Mali-G71}} [[IGP]].
  
  
 
{{unknown features}}
 
{{unknown features}}

Revision as of 15:40, 3 March 2017

Template:mpu

Surge S2 is a 64-bit octa-core performance ARM system-on-chip designed by Xiaomi set to be introduced in late 2017. The Surge S2 is Xiaomi flagship processor. This chip incorporates eight cores in a big.LITTLE configuration with four high-performance Cortex-A73 cores operating at up to 2.7 GHz with another four low-power Cortex-A53 cores operating at 2 GHz. This processor is fabricated on TSMC's 10 nm process and incorporates a Mali-G71 IGP.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.