x86
Instruction Set Architecture

General

• History
• Families

Variants

• x86-16
• x86-32
• x86-64

Topics

• Instructions
• Addressing Modes
• Registers
• Model-Specific Register
• Assembly
• Interrupts
• Micro-Ops
• Timer
• Calling Convention
• Microarchitectures
• CPUID

CPUIDs

• AMD's CPUIDs
• Intel's CPUIDs

Modes

• Real
• Protected
• Long

Extensions(all)

• 3DNow!
• ABM
• ADX
• AES
• AMX
• AVX
• AVX2
• AVX-512
• BMI1
• BMI2
• CLMUL
• E3DNow!
• EMMX
• F16C
• FMA3
• FMA4
• FPU
• MKTME
• MMX
• MPX
• PMEM
• PREFETCH
• RdRAND
• SEV
• SGX
• SHA
• SME
• SMM
• SMX
• SSE
• SSE2
• SSE3
• SSE4.1
• SSE4.2
• SSE4a
• SSE5
• SSSE3
• TBM
• TME
• TSME
• TSX
• XOP

Secure Memory Encryption (SME) is an x86 instruction set extension introduced by AMD for page-granular memory encryption support using a single ephemeral key. A subset of SME, Transparent SME (SME), is a more limited form of SME used to transparently encrypt the full physical memory.