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| | {{x86 title|Persistent Memory Extensions}}{{x86 isa main}} | | {{x86 title|Persistent Memory Extensions}}{{x86 isa main}} |
| − | '''Persistent memory {{x86|extensions}}''' ('''PMEM''') are a set of [[x86]] instructions designed to improve the usability of working with [[storage-class memory]]. | + | '''Persistent memory {{x86|extensions}}''' are a set of [[x86]] instructions designed to improve the usability of working with [[storage-class memory]]. |
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| − | == Overview ==
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| − | [[Intel]] adopted the [[SNIA]] [[NVM Programming Model]] for working with persistent memory. This model allows for {{snia|direct access}} (DAX) using byte-addressable operations (i.e., load/store), however, the persistence of the data in the [[cache]] is not guaranteed until it has entered the [[persistence domain]]. [[x86]] provides a set of instructions for [[flushing]] [[cache lines]] in a more optimized way. In addition to existing [[x86]] instructions such as non-temporal stores, <code>CLFLUSH</code>, and <code>WBINVD</code> (kernel only), two new instructions were added:
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| − | {| class="wikitable"
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| − | ! Instruction !! Description
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| − | | <code>CLFLUSHOPT</code> || Optimized CLFLUSH; Behaves similarly to <code>CLFLUSH</code> but without the serialization, thereby optimized for performance by allowing for some concurrency when executing multiple CLFLUSHOPT instructions back-to-back.
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| − | | <code>CLWB</code> || Cache line write back; behaves similarly to <code>CLFLUSHOPT</code> but keeps the cache line valid (i.e., the cache line is flushed and then marked as no longer dirty) thereby optimized for performance by keeping the line in the cache, increasing the chance of a [[cache hit]].
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| − | |}
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| − | Both of the new instructions must follow by a <code>SFENCE</code> to ensure all flushes are completed before continuing.
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| − | == Detection ==
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| − | {| class="wikitable"
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| − | ! colspan="2" | {{x86|CPUID}} !! rowspan="2" | Instruction Set
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| − | |-
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| − | ! Input !! Output
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| − | |-
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| − | | rowspan="2" | EAX=07H, ECX=0 || EBX[bit 23] || CLFLUSHOPT
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| − | |-
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| − | | EBX[bit 24] || CLWB
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| − | |}
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| − | | |
| − | == Microarchitecture support ==
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| − | {| class="wikitable"
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| − | ! rowspan="2" | Instruction !! colspan="2" | Introduction
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| − | |-
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| − | ! [[Intel]] !! [[AMD]]
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| − | |-
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| − | | <code>CLFLUSHOPT</code> || {{intel|Skylake (server)|l=arch}}<br>{{intel|Skylake (client)|l=arch}}<br>{{intel|Goldmont|l=arch}} || {{amd|Zen|l=arch}}
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| − | |-
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| − | | <code>CLWB</code> || {{intel|Skylake (server)|l=arch}}<br>{{intel|Ice Lake (client)|l=arch}} || {{amd|Zen 2|l=arch}}
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| − | |}
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| − | | |
| − | == Intrinsic functions ==
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| − | <source lang=asm>
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| − | #include <immintrin.h>
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| − | | |
| − | # clflushopt
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| − | void _mm_clflushopt (void const * p)
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| − | | |
| − | # clwb
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| − | void _mm_clwb (void const * p)
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| − | </source>
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| − | | |
| − | == See also ==
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| − | * {{snia|NVM Programming Model}}
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| − | | |
| − | [[Category:x86_extensions]]
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