From WikiChip
Difference between revisions of "x86/clzero"
< x86

(Created page with "{{x86 title|CLZERO}}{{x86 isa main}} '''CLZERO''' is an AMD vendor specific {{x86|extensions|x86 instruction}} introduced with the {{amd|Zen|l=arch}} microarchitecture. == Ov...")
 
(No difference)

Latest revision as of 00:43, 4 December 2019

CLZERO is an AMD vendor specific x86 instruction introduced with the Zen microarchitecture.

Overview[edit]

CLZERO clears the cache line specified by the logical address in the RAX register by writing a zero to every byte in the line. The instruction uses an implied non-temporal memory type, similar to a streaming store, and uses the write combining protocol to minimize cache pollution. CLZERO is weakly-ordered with respect to other instructions that operate on memory. It executes at any privilege level and performs all the segmentation and paging checks that a store of the specified cache line would perform.

Motivation[edit]

The instruction is intended to recover from some otherwise fatal Machine Check Architecture (MCA) errors caused by uncorrectable corrupt memory. The instruction is non-cachable, unlike the PowerPC DCBZ instruction. It can not be used to allocate a cache line without a memory access, and should not be used to quickly zero memory.

Background: The Zen microarchitecture supports cache poisoning. When this feature is enabled and the memory controller detects an uncorrectable error in a data word read from ECC-capable memory, it will not cause an exception which inevitably leads to a kernel panic and system shutdown, but marks the affected bytes as "poisoned" and passes the data on to the cache controller, to be stored in the cache. Only when a CPU core attempts to read the poisoned bytes of the cache line is an exception triggered, creating an opportunity for the operating system to contain the problem and kill only the affected process. The CLZERO instruction can be used to atomically clear the whole cache line and any poisoned status.

The execution path of CLZERO is Store Queue, Store Commit, Write Combining Buffer, L2 Cache, Scalable Data Fabric, Memory.

References[edit]

  • AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions, revision 3.28
  • Game Developers Conference, March 20th 2019, AMD Ryzen Processor Software Optimization presentation by Ken Mitchell