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Difference between revisions of "umich/microarchitectures/vanilla-5"
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{{title|Vanilla-5 - Microarchitectures}} | {{title|Vanilla-5 - Microarchitectures}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=CPU | ||
| + | |name=Vanilla-5 | ||
| + | |designer=University of Michigan | ||
| + | |designer 2=University of California | ||
| + | |designer 3=Cornell University | ||
| + | |designer 4=University of California | ||
| + | |manufacturer=TSMC | ||
| + | |process=16 nm | ||
| + | |type=Pipelined | ||
| + | |oooe=No | ||
| + | |speculative=No | ||
| + | |renaming=No | ||
| + | |stages=5 | ||
| + | |decode=1 | ||
| + | |isa=RISC-V | ||
| + | |extension=Integer | ||
| + | |extension 2=Multiply | ||
| + | |l1i=4 KiB | ||
| + | |l1i per=core | ||
| + | |l1d=4 KiB | ||
| + | |l1d per=core | ||
| + | }} | ||
'''Vanilla-5''' is a custom [[RISC-V]] core microarchitecture designed specifically for the {{\\|Celerity}} SoC. | '''Vanilla-5''' is a custom [[RISC-V]] core microarchitecture designed specifically for the {{\\|Celerity}} SoC. | ||
Revision as of 23:42, 12 January 2020
| Edit Values | |
| Vanilla-5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | University of Michigan, University of California, Cornell University, University of California |
| Manufacturer | TSMC |
| Process | 16 nm |
| Pipeline | |
| Type | Pipelined |
| OoOE | No |
| Speculative | No |
| Reg Renaming | No |
| Stages | 5 |
| Decode | 1 |
| Instructions | |
| ISA | RISC-V |
| Extensions | Integer, Multiply |
| Cache | |
| L1I Cache | 4 KiB/core |
| L1D Cache | 4 KiB/core |
Vanilla-5 is a custom RISC-V core microarchitecture designed specifically for the Celerity SoC.
Facts about "Vanilla-5 - Microarchitectures"
| codename | Vanilla-5 + |
| designer | University of Michigan +, University of California + and Cornell University + |
| full page name | umich/microarchitectures/vanilla-5 + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Vanilla-5 + |
| pipeline stages | 5 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |
