Difference between revisions of "umich/microarchitectures/celerity"

	Edit Values
	Celerity µarch
	General Info
Arch Type	CPU
Designer	University of Michigan, University of Washington, Cornell University, University of California
Manufacturer	TSMC
Process	16 nm
	Instructions
ISA	RISC-V
Extensions	Integer, Multiply

Latest revision as of 01:14, 21 January 2020

Celerity is a custom RISC-V-based neural processor microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.

Etymology[edit]

Celerity means 'swiftness of movement' which is the intended purpose of the architecture.

Process technology[edit]

Celerity is fabricated on TSMC 16 nm process.

Overview[edit]

Celerity is a university-based research chip designed for the acceleration of artificial intelligence. The design and implementation of the chip was said to have taken just nine months through the use of agile development and leveraging existing open-source code. The design is intended to allow enough flexibility as AI workloads continue to evolve. Designed for TSMC 16 nm process, the chip integrates three separate tiers of architectures, each is progressively more specialized, less flexible, but more power-efficient. The first tier, the general-purpose tier, integrates five powerful RISC-V Rocket cores capable of running an operating system and managing the rest of the SoC. The second tier, the massively parallel tier, integrates a massive array of 496 parallel highly-efficient, but simple, RISC-V Vanilla-5 cores. The last tier is the specialization tier which integrates a specialized custom BNN accelerator.