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== Overview == | == Overview == | ||
LIPINCON is an interconnect architecture designed for [[chiplet]] designs with advanced packaging technologies such as {{tsmc|InFO}} and {{tsmc|CoWoS}}. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins. | LIPINCON is an interconnect architecture designed for [[chiplet]] designs with advanced packaging technologies such as {{tsmc|InFO}} and {{tsmc|CoWoS}}. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins. | ||
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== Bibliography == | == Bibliography == | ||
* TSMC, MS Lin et a., 2013 VLSI Symposium | * TSMC, MS Lin et a., 2013 VLSI Symposium |