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== Overview ==
 
== Overview ==
 
LIPINCON is an interconnect architecture designed for [[chiplet]] designs with advanced packaging technologies such as {{tsmc|InFO}} and {{tsmc|CoWoS}}. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins.
 
LIPINCON is an interconnect architecture designed for [[chiplet]] designs with advanced packaging technologies such as {{tsmc|InFO}} and {{tsmc|CoWoS}}. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins.
 
== Architecture ==
 
The architecture is designed to take advantage of an advanced packaging technology such as {{tsmc|CoWoS}} whereby multiple dies are stacked on a silicon interposer communicating by PHYs over short wires. LIPINCON uses two different types of PHYs: '''PHYC''' for an SoC die and '''PHYM''' for a memory, transceiver, or similar kind of dies. The clock source in the PHYM relies on one system clock propagated from PHYC. There is no [[phase-locked loop|PLL]]/[[delay-locked loop|DLL]] function blocks built in PHYM because it assumes that the SoC will generally be fabricated on a more advanced node and is therefore capable of handling this more efficiently than a memory/transceiver that may be made on a more mature node.
 
  
 
== Bibliography ==
 
== Bibliography ==
 
* TSMC, MS Lin et a., 2013 VLSI Symposium
 
* TSMC, MS Lin et a., 2013 VLSI Symposium

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