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Information for "socionext/sc2a11"

Basic information

Display titleSC2A11 - Socionext
Default sort keySC2A11, socionext
Page length (in bytes)1,632
Page ID11904
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page4
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorInject (talk | contribs)
Date of page creation02:09, 4 December 2016
Latest editor93.218.254.190 (talk)
Date of latest edit14:00, 15 February 2019
Total number of edits26
Total number of distinct authors5
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

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Facts about "SC2A11 - Socionext"
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus typeAMBA +
core count24 +
core nameCortex-A53 +
designerSocionext + and ARM Holdings +
first announcedNovember 14, 2016 +
first launched2017 +
full page namesocionext/sc2a11 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l1d$ description4-way set associative +
l1d$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l1i$ description2-way set associative +
l1i$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l2$ description16-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate3000 +
main imageFile:SC2A11 IMG01.jpg +
market segmentServer +, Networking + and IoT +
max cpu count64 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (55.315 GB/s, 32,552.96 MiB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes4 +
microarchitectureCortex-A53 +
model numberSC2A11 +
nameSocionext SC2A11 +
supported memory typeDDR4-2133 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technologyCMOS +
thread count24 +
word size64 bit (8 octets, 16 nibbles) +