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From WikiChip
7 Series - Microarchitectures - SiFive
< sifive
| Edit Values | |
| 7 Series µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | SiFive |
| Manufacturer | TSMC, GlobalFoundries |
| Introduction | October 21, 2018 |
| Core Configs | 1, 2, 4, 6, 8 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Stages | 8 |
| Decode | 2 |
| Instructions | |
| ISA | RISC-V |
| Cores | |
| Core Names | E76, E76-MC, S76, S76-MC, U74, U74-MC |
| Succession | |
7 Series is a series of high-performance RISC-V IP cores designed by SiFive.
Retrieved from "https://en.wikichip.org/w/index.php?title=sifive/microarchitectures/7_series&oldid=83851"
Facts about "7 Series - Microarchitectures - SiFive"
| codename | 7 Series + |
| core count | 1 +, 2 +, 4 +, 6 + and 8 + |
| designer | SiFive + |
| first launched | October 21, 2018 + |
| full page name | sifive/microarchitectures/7 series + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + and GlobalFoundries + |
| microarchitecture type | CPU + |
| name | 7 Series + |
| pipeline stages | 8 + |
