Revision history of "sifive/microarchitectures/7 series"

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(cur | prev) 09:16, 28 November 2018‎ 46.109.192.167 (talk)‎ . . (4,270 bytes) (0)‎ . . (→‎Cores: Fixed a spelling mistake: compArable) (undo)
(cur | prev) 00:03, 5 November 2018‎ David (talk | contribs)‎ . . (4,270 bytes) (+126)‎ . . (→‎Key changes from {{\\|5 Series}}) (undo)
(cur | prev) 23:30, 4 November 2018‎ David (talk | contribs)‎ . . (4,144 bytes) (+421)‎ . . (→‎Cluster) (undo)
(cur | prev) 23:26, 4 November 2018‎ David (talk | contribs)‎ . . (3,723 bytes) (+1,211)‎ . . (→‎Core) (undo)
(cur | prev) 22:36, 4 November 2018‎ David (talk | contribs)‎ . . (2,512 bytes) (+29)‎ . . (→‎Key changes from {{\\|5 Series}}) (undo)
(cur | prev) 22:34, 4 November 2018‎ David (talk | contribs)‎ . . (2,483 bytes) (+1,822)‎ . . (undo)
(cur | prev) 21:00, 4 November 2018‎ David (talk | contribs)‎ . . (661 bytes) (+514)‎ . . (undo)
(cur | prev) 20:56, 4 November 2018‎ David (talk | contribs)‎ . . (147 bytes) (+147)‎ . . (7 series)

codename	7 Series +
core count	1 +, 2 +, 4 +, 6 + and 8 +
designer	SiFive +
first launched	October 21, 2018 +
full page name	sifive/microarchitectures/7 series +
instance of	microarchitecture +
instruction set architecture	RISC-V +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture type	CPU +
name	7 Series +
pipeline stages	8 +

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