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Difference between revisions of "risc-v/standard extensions"
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== Overview == | == Overview == | ||
| − | By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}}. Extensions can be implemented and omitted as desired. Those extensions are: | + | By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}} such as [[floating point]] and operations and [[bit]] [[bit manipulation|manipulation]]. Extensions can be implemented and omitted as desired. Those extensions are: |
* '''{{risc-v|A}}''' - Atomic instructions | * '''{{risc-v|A}}''' - Atomic instructions | ||
Revision as of 00:42, 12 December 2017
RISC-V
Instruction Set Architecture
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).
Overview
By default, only the core ISA must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the core ISA such as floating point and operations and bit manipulation. Extensions can be implemented and omitted as desired. Those extensions are:
- A - Atomic instructions
- B - Bit manipulation instructions
- C - Compressed instructions
- D - Double-precision floating-point instructions
- F - Single-precision floating-point instructions
- J - Dynamically translated languages
- L - Decimal floating point instructions
- M - Integer multiplication and division instructions
- N - User-level interrupt instructions
- P - Packed-SIMD instructions
- Q - Quad-precision floating-point instructions
- T - Transactional Memory instructions
- V - Vector operations instructions
