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(Created page with "{{risc-v title|Standard Extensions}}{{risc-v isa main}} RISC-V has standardized a series of '''standard extensions''' beyond the integer base instructions which can be impleme...")
 
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{{risc-v title|Standard Extensions}}{{risc-v isa main}}
 
{{risc-v title|Standard Extensions}}{{risc-v isa main}}
RISC-V has standardized a series of '''standard extensions''' beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals.
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RISC-V has standardized a series of '''standard extensions''' beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).
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== Overview ==
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By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}}. Extensions can be implemented and omitted as desired. Those extensions are:
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* '''{{risc-v|M}}''' - Integer multiplication and division instructions
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* '''{{risc-v|A}}''' - Atomic instructions
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* '''{{risc-v|F}}''' - Single-precision floating-point instructions
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* '''{{risc-v|D}}''' - Double-precision floating-point instructions
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* '''{{risc-v|Q}}''' - Quad-precision floating-point instructions
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* '''{{risc-v|L}}''' - Decimal floating point instructions
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* '''{{risc-v|C}}''' - Compressed instructions
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* '''{{risc-v|B}}''' - Bit manipulation instructions
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* '''{{risc-v|J}}''' - Dynamically translated languages
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* '''{{risc-v|T}}''' - Transactional Memory instructions
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* '''{{risc-v|P}}''' - Packed-SIMD instructions
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* '''{{risc-v|V}}''' - Vector operations instructions
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* '''{{risc-v|N}}''' - User-level interrupt instructions

Revision as of 00:33, 12 December 2017

RISC-V
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics

v · d · e

RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

Overview

By default, only the core ISA must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the core ISA. Extensions can be implemented and omitted as desired. Those extensions are:

  • M - Integer multiplication and division instructions
  • A - Atomic instructions
  • F - Single-precision floating-point instructions
  • D - Double-precision floating-point instructions
  • Q - Quad-precision floating-point instructions
  • L - Decimal floating point instructions
  • C - Compressed instructions
  • B - Bit manipulation instructions
  • J - Dynamically translated languages
  • T - Transactional Memory instructions
  • P - Packed-SIMD instructions
  • V - Vector operations instructions
  • N - User-level interrupt instructions