Editing risc-v/standard extensions

{{risc-v title|Standard Extensions}}{{risc-v isa main}}
RISC-V has standardized a series of '''standard extensions''' beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

== Overview ==
By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}}. Extensions can be implemented and omitted as desired. Those extensions are:

{| class="wikitable"
|-
! Name !! Description !! Version !! Status !! Instruction Count
|-
| RV32I || Base Integer Instruction Set - 32-bit || 2.1 || Frozen || 49
|-
| RV32E || Base Integer Instruction Set (embedded) - 32-bit, 16 registers || 1.9 || Open || Same as RV32I
|-
| RV64I || Base Integer Instruction Set - 64-bit || 2.0 || Frozen || 14
|-
| RV128I || Base Integer Instruction Set - 128-bit || 1.7 || Open || 14
|-
! colspan=5 | Extension
|-
| M || Standard Extension for Integer Multiplication and Division || 2.0 || Frozen || 8
|-
| A || Standard Extension for Atomic Instructions || 2.0 || Frozen || 11
|-
| F || Standard Extension for Single-Precision Floating-Point || 2.0 || Frozen || 25
|-
| D || Standard Extension for Double-Precision Floating-Point || 2.0 || Frozen || 25
|-
| G || Shorthand for the base and above extensions || n/a || n/a || n/a
|-
| Q || Standard Extension for Quad-Precision Floating-Point || 2.0 || Frozen || 27
|-
| L || Standard Extension for Decimal Floating-Point || 0.0 || Open || Undefined Yet
|-
| C || Standard Extension for Compressed Instructions || 2.0 || Frozen || 36
|-
| B || Standard Extension for Bit Manipulation || 0.90 || Open || 42
|-
| J || Standard Extension for Dynamically Translated Languages || 0.0 || Open || Undefined Yet
|-
| T || Standard Extension for Transactional Memory || 0.0 || Open || Undefined Yet
|-
| P ||| Standard Extension for Packed-SIMD Instructions || 0.1 || Open || Undefined Yet
|-
| V || Standard Extension for Vector Operations || 0.7 || Open || 186
|-
| N || Standard Extension for User-Level Interrupts || 1.1 || Open || 3
|-
| H || Standard Extension for Hypervisor || 1.0 || Frozen || 2
|-
| S || Standard Extension for Supervisor-level Instructions || 1.12 || Open || 7
|}

== Naming Convention ==
RISC-V defines an exact order that must be used to define the RISC-V ISA subset:

: <code>RV [32, 64, 128]</code> <code>I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N</code>

For example, <code>RV32IMAFDQC</code> is legal, whereas <code>RV32IMAFDCQ</code> is not.